Chia-Chun Tsai

Adv. Eng. Informatics, 2021

2020

3D Hand Gesture Recognition for Drone Control in Unity<sup>*</sup>.

[BibT_eX]

[DOI]

Chih-Chia Kuo

Yen-Lun Chen

Proceedings of the 16th IEEE International Conference on Automation Science and Engineering, 2020

2019

Performance Improvement for Stacked-Layer Data Bus Reconstruction on Complete Timing Period.

[BibT_eX]

[DOI]

Proceedings of the 2019 International SoC Design Conference, 2019

2018

Embedded bus switches on 3D data bus for critical access time reduction.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

2017

Minimizing Critical Access Time for 3D Data Bus Based on Inserted Bus Switches and Repeaters.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016

Hybrid Architecture Design for Calculating Variable-Length Fourier Transform.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

2015

Improved PSO based home energy management systems integrated with demand response in a smart grid.

[BibT_eX]

[DOI]

Proceedings of the IEEE Congress on Evolutionary Computation, 2015

2013

A reduced Li-Ion battery charger for portable applications.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Conference on Natural Computation, 2013

Low Complexity Digit-Serial Multiplier over GF(2^m) Using Karatsuba Technology.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on Complex, 2013

2012

Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

Discharge-path-based antenna effect detection and fixing for X-architecture clock tree.

[BibT_eX]

[DOI]

Integr., 2012

Micro fuel cell power management circuit design for portable devices.

[BibT_eX]

[DOI]

Tsung-Ming Liu

Proceedings of the 9th International Conference on Fuzzy Systems and Knowledge Discovery, 2012

2011

The RF Circuit Design of Power and Data Contactless Transmission for ISO/IEC 14443-2 Type B.

[BibT_eX]

[DOI]

Sheng-Bin Dai

J. Circuits Syst. Comput., 2011

Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration.

[BibT_eX]

[DOI]

Chung-Chieh Kuo

Integr., 2011

Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement.

[BibT_eX]

[DOI]

Chung-Chieh Kuo

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2010

Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2010

Antenna Violation Avoidance/Fixing for X-clock routing.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Double-via insertion enhanced X-architecture clock routing for reliability.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

The Design of a Li-ion Battery Charger Based on Multimode LDO Technology.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2009

A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters.

[BibT_eX]

[DOI]

Kai-Wei Hong

J. Circuits Syst. Comput., 2009

Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion.

[BibT_eX]

[DOI]

Jan-Ou Wu

Circuits Syst. Signal Process., 2009

2008

GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay.

[BibT_eX]

[DOI]

Jan-Ou Wu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

X-clock routing based on pattern matching.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Layer assignment considering manufacturability in X-architecture clock tree.

[BibT_eX]

[DOI]

Proceedings of 8th IEEE International Conference on Computer and Information Technology, 2008

2007

Zero-Skew Driven Buffered RLC Clock Tree Construction.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems.

[BibT_eX]

Proceedings of the International MultiConference of Engineers and Computer Scientists 2007, 2007

Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2007), 2007

2006

Using Stack Reconstruction on RTL Orthogonal Scan Chain Design.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2006

Coupling aware RLC-based clock routings for crosstalk minimization.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A single chip image sensor embedded smooth spatial filter with A/D conversion.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Inductance extraction for general interconnect structures.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion.

[BibT_eX]

[DOI]

Yang-Hsin Fan

Proceedings of the First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August, 2006

Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

A new low-power turbo decoder using HDA-DHDD stopping iteration.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A new CCII-based pipelined analog to digital converter.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Zero-Skew Driven for RLC Clock Tree Construction in SoC.

[BibT_eX]

[DOI]

Proceedings of the Third International Conference on Information Technology and Applications (ICITA 2005), 2005

2004

An embedded analog spatial filter design of the current-mode CMOS image sensor.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2004

RCGES: Retargetable Code Generation for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004

2000

Efficient routability check algorithms for segmented channel routing.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2000

1999

An Even Wiring Approach to the Ball Grid Array Package Routing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design, 1999

An Efficient Two-Level Partitioning Algorithm for VLSI Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

An Automatic Router for the Pin Grid Array Package.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

NEWS: a net-even-wiring system for the routing on a multilayer PGA package.

[BibT_eX]

[DOI]

Chwan-Ming Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997

Hmap: a fast mapper for EPGAs using extended GBDD hash tables.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1997

1996

Performance driven bus buffer insertion.

[BibT_eX]

[DOI]

De-Yu Kao

Chung-Kuan Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995

Performance driven multiple-source bus synthesis using buffer insertion.

[BibT_eX]

[DOI]

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

A Linear Time Algorithm for Planar Moat Routing.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 1994

1992

An H-V alternating router.

[BibT_eX]

[DOI]

Wu-Shiung Feng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Minimum Partition for the Space Region of VLSI Layout.

[BibT_eX]

[DOI]

Pei-Yung Hsiao

Chiao-Yi Lin

Proceedings of the Fifth International Conference on VLSI Design, 1992

1991

A knowledge-based program for compacting mask layout of integrated circuits.

[BibT_eX]

[DOI]

Comput. Aided Des., 1991

1990

An <i>H-V</i> Tile-Expansion Router.

[BibT_eX]

[DOI]

Wu-Shiung Feng

J. Inf. Sci. Eng., 1990

Generalized terminal connectivity problem for multilayer layout scheme.

[BibT_eX]

[DOI]

Wu-Shiung Feng

Comput. Aided Des., 1990

A new plane-sweep algorithm based on spatial data structure for overlapped rectangles in 2-D plane.

[BibT_eX]

[DOI]

Pei-Yung Hsiao