Chia-Chih Yen

According to our database, Chia-Chih Yen authored at least 14 papers between 2001 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification.

Yi-An Chen, Gung-Yu Pan, Che-Hua Shih, Yen-Chin Liao, Chia-Chih Yen, Hsie-Chia Chang

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Failure Root Cause Analysis Automation on Functional Simulation Regressions.

Chia-Chih Jack Yen

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2014

Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog.

An-Che Cheng, Chia-Chih Jack Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou

ACM Trans. Design Autom. Electr. Syst., 2014

2012

A formal method to improve SystemVerilog functional coverage.

An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

2010

FSM-Based Formal Compliance Verification of Interface Protocols.

Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou

J. Inf. Sci. Eng., 2010

2008

A General Failure Candidate Ranking Framework for Silicon Debug.

Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

2006

An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging.

Chia-Chih Yen, Jing-Yang Jou

IEEE Trans. Computers, 2006

Diagnosing Silicon Failures Based on Functional Test Patterns.

Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu

Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

2005

An optimum algorithm for compacting error traces for efficient functional debugging.

Chia-Chih Yen, Jing-Yang Jou

Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

2004

A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation.

Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen

IEEE Des. Test Comput., 2004

Enhancing sequential depth computation with a branch-and-bound algorithm.

Chia-Chih Yen, Jing-Yang Jou

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

On compliance test of on-chip bus for SOC.

Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2002

A Practical Approach to Cycle Bound Estimation for Property Checking.

Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

2001

Automatic Functional Vector Generation Using the Interacting FSM Model.

Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001