Chia-Chen Chou
According to our database1,
Chia-Chen Chou
authored at least 10 papers
between 2010 and 2018.
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Collaborative distances:
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Bibliography
2018
ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
2017
BATMAN: techniques for maximizing system bandwidth of memory systems with stacked-DRAM.
Proceedings of the International Symposium on Memory Systems, 2017
2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
2015
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015
2014
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
2010
An initial attempt to improve spoken term detection by learning optimal weights for different indexing features.
Proceedings of the IEEE International Conference on Acoustics, 2010