Chi-Yi Yeh

According to our database1, Chi-Yi Yeh authored at least 1 paper in 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2007
Using power gating techniques in area-array SoC floorplan design.
Proceedings of the 2007 IEEE International SOC Conference, 2007


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