Chi-Wen Chou
According to our database1,
Chi-Wen Chou
authored at least 3 papers
between 2006 and 2010.
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Collaborative distances:
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Bibliography
2010
Low power and high speed multiplier design with row bypassing and parallel architecture.
Microelectron. J., 2010
2006
A Low-Power Multiplier with Bypassing Logic and Operand Decomposition.
Proceedings of the International MultiConference of Engineers and Computer Scientists 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006