Chi-Shin Chang
According to our database1,
Chi-Shin Chang
authored at least 5 papers
between 2011 and 2013.
Collaborative distances:
Collaborative distances:
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Bibliography
2013
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011