Chi-Ray Huang

According to our database, Chi-Ray Huang authored at least 7 papers between 2012 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM.

Chi-Ray Huang, Lih-Yih Chiou

IEEE Trans. Very Large Scale Integr. Syst., 2021

2019

A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs.

Lih-Yih Chiou, Chi-Ray Huang, Chang-Chieh Cheng, Jing-Yu Huang, Wei-Suo Ling

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2018

Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation.

Chi-Ray Huang, Lih-Yih Chiou

IET Circuits Devices Syst., 2018

Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme.

Chi-Ray Huang, Kuan-Lin Wu, Chung-Han Wu, Lih-Yih Chiou

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2014

An ultra-low-power adaptive-body-bias control for subthreshold circuits.

Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits.

Lih-Yih Chiou, Chi-Ray Huang, Ming-Hung Wu

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2012

Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion.

Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012