Chi-Nan Chuang

According to our database, Chi-Nan Chuang authored at least 7 papers between 2006 and 2014.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2014

A wide-range and fast-locking frequency synthesizer for Wimax and WLAN applications.

Chun-Yen Wu, Chi-Nan Chuang, Chao-Chyun Chen, I-Chyn Wey

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

2009

A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop.

Chi-Nan Chuang, Shen-Iuan Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2009

2008

A 3-8 GHz Delay-Locked Loop With Cycle Jitter Calibration.

Chi-Nan Chuang, Shen-Iuan Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2008

2007

A Time-Constant Calibrated Phase-Locked Loop With a Fast-Locked Time.

Sung-Rung Han, Chi-Nan Chuang, Shen-Iuan Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A 0.5-5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump.

Chi-Nan Chuang, Shen-Iuan Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology.

Chi-Nan Chuang, Shen-Iuan Liu

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology.

Chi-Nan Chuang, Shen-Iuan Liu

IEICE Trans. Electron., 2006