Chi-Lun Tsai

According to our database, Chi-Lun Tsai authored at least 2 papers between 2013 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations.

Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2016

2013

Variation-aware and adaptive-latency accesses for reliable low voltage caches.

Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013