Chi-Hsiang Weng

According to our database, Chi-Hsiang Weng authored at least 1 paper in 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window.

Chien-An Lai, Chung-Cheng Chou, Chi-Hsiang Weng, Zheng-Jun Lin, Pei-Ling Tseng, Chien-Fan Wang, Chih-Chen Wang, Chin-I Su, Wei-Chi Chen, Yu-Cheng Lin, Tong-Chern Ong, Chi Chang, Yu-Der Chih, Tsung-Yung Jonathan Chang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018