Chi-Feng Wu

According to our database, Chi-Feng Wu authored at least 29 papers between 1999 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model.

Yu-Ju Shih, Chih-Tsun Huang, Jing-Jia Liou, Jyu-Yuan Lai, Chih-Wea Wang, Chi-Feng Wu

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2014

Apply high-level synthesis design and verification methodology on floating-point unit implementation.

Chia-I Chen, Chin-Yeh Yu, Yen-Ju Lu, Chi-Feng Wu

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Mask-cost-aware ECO routing^∗.

Hsi-An Chien, Zhen-Yu Peng, Yun-Ru Wu, Ting-Hsiung Wang, Hsin-Chang Lin, Chi-Feng Wu, Ting-Chi Wang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Case study of yield learning through in-house flow of volume diagnosis.

Pei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012

Applying a Functional Neurofuzzy Network to Real-Time Lane Detection and Front-Vehicle Distance Measurement.

Chi-Feng Wu, Cheng-Jian Lin, Chi-Yung Lee

IEEE Trans. Syst. Man Cybern. Part C, 2012

Locating Text in Images Based on the Smooth Gray-Level Detection.

Shiueng-Bien Yang, Chi-Feng Wu

Int. J. Image Graph., 2012

Test for more than pass/fail using on-chip temperature sensor.

Chih-Wea Wang, Chen-Tung Lin, Chun-Chieh Hsu, Ching-Tung Wu, Chi-Feng Wu

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011

A functional neural fuzzy network for classification applications.

Chi-Feng Wu, Cheng-Jian Lin, Chi-Yung Lee

Expert Syst. Appl., 2011

2009

Application of neural networks and genetic algorithms to the screening for high quality chips.

Chenn-Jung Huang, You-Jia Chen, Chi-Feng Wu, Yi-An Huang

Appl. Soft Comput., 2009

A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design.

Hsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu

Proceedings of the 2009 IEEE International Test Conference, 2009

2007

CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs.

Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu

Proceedings of the 16th Asian Test Symposium, 2007

2004

A novel approach to enable decorrelating multiuser detection without matrix inversion operations.

Hsiao-Hwa Chen, Chi-Feng Wu

Int. J. Commun. Syst., 2004

2003

Isotropic air-interface technologies for fourth generation wireless communications.

Hsiao-Hwa Chen, Jin-Xiao Lin, Shin-Wei Chu, Chi-Feng Wu, Guo-Sheng Chen

Wirel. Commun. Mob. Comput., 2003

Built-in redundancy analysis for memory yield improvement.

Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu

IEEE Trans. Reliab., 2003

2002

Fault simulation and test algorithm generation for random accessmemories.

Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM.

Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin

J. Electron. Test., 2002

Image Processing Techniques for Wafer Defect Cluster Identification.

Chenn-Jung Huang, Chua-Chin Wang, Chi-Feng Wu

IEEE Des. Test Comput., 2002

Flash Memory Built-In Self-Test Using March-Like Algorithm.

Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories.

Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu

Proceedings of the 38th Design Automation Conference, 2001

A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.

Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Testing and Diagnosing Dynamic Reconfigurable FPGA.

Chi-Feng Wu, Cheng-Wen Wu

VLSI Design, 2000

Single-ended SRAM with high test coverage and short test time.

Chua-Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, Chia-Hsiung Kao

IEEE J. Solid State Circuits, 2000

Simulation-Based Test Algorithm Generation for Random Access Memories.

Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Error Catch and Analysis for Semiconductor Memories Using March Tests.

Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

A built-in self-test and self-diagnosis scheme for embedded SRAM.

Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Collaboration between Industry and Academia in Test Research.

Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

A Programmable BIST Core for Embedded DRAM.

Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang

IEEE Des. Test Comput., 1999

RAMSES: A Fast Memory Fault Simulator.

Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Testing Interconnects of Dynamic Reconfigurable FPGAs.

Chi-Feng Wu, Cheng-Wen Wu

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999