Chi-An Wu

According to our database1, Chi-An Wu authored at least 16 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Invited Paper: 2023 ICCAD CAD Contest Problem A: Multi-Bit Large-Scale Boolean Matching.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022
2022 CAD Contest Problem A: Learning Arithmetic Operations from Gate-Level Circuit.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021
2021 CAD Contest Problem A: Functional ECO with Behavioral Change Guidance Invited Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020
ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited Talk.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
2019 CAD Contest: Logic Regression on High Dimensional Boolean Space.
Proceedings of the International Conference on Computer-Aided Design, 2019

2017
ICCAD-2017 CAD contest in resource-aware patch generation.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
ICCAD-2016 CAD contest in non-exact projective NPNP boolean matching and benchmark suite.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
ICCAD-2015 CAD Contest in Large-scale Equivalence Checking and Function Correction and Benchmark Suite.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

ICCAD-2014 CAD contest in simultaneous CNF encoder optimization with SAT solver setting selection and benchmark suite.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2011
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method.
Proceedings of the Design, Automation and Test in Europe, 2011

Interpolation-based incremental ECO synthesis for multi-error logic rectification.
Proceedings of the 48th Design Automation Conference, 2011

A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2009
Interpolant generation without constructing resolution graph.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

SAT-controlled redundancy addition and removal: a novel circuit restructuring technique.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2007
QuteSAT: a robust circuit-based SAT solver for complex circuit structure.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007


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