Chewnpu Jou
According to our database1,
Chewnpu Jou
authored at least 28 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
2010
2012
2014
2016
2018
2020
2022
2024
0
1
2
3
4
5
2
1
1
1
1
1
1
1
3
3
2
2
4
1
4
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2019
A 0.85mm<sup>2</sup> 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD<sub>2</sub> Self-Suppression and Pulling Mitigation.
IEEE J. Solid State Circuits, 2019
A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications.
IEEE J. Solid State Circuits, 2019
A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network.
IEEE J. Solid State Circuits, 2017
2016
A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm.
IEEE J. Solid State Circuits, 2016
A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm.
Proceedings of the ESSCIRC Conference 2015, 2015
Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c TRX.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010