Chetan Vudadha

Goli Naga Sandesh

Circuits Syst. Signal Process., September, 2024

Design of Resource Efficient Binary and Floating Point Comparator Using FPGA Primitive Instantiation.

[BibT_eX]

[DOI]

Vikas Shivakumar

J. Circuits Syst. Comput., January, 2024

Design of CNFET-based Ternary Conditional Sum Adders using Binary Carry Propagation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

Power efficient designs of CNTFET-based ternary SRAM.

[BibT_eX]

[DOI]

Goli Naga Sandesh

Microelectron. J., September, 2023

2022

Optimization of Reversible Circuits Using Gate Pair Classification.

[BibT_eX]

[DOI]

SN Comput. Sci., 2022

Design of CNTFET-based Ternary Logic circuits using Low power Encoder.

[BibT_eX]

[DOI]

Siddharth T

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2020

A Novel Low Power Ternary Multiplier Design using CNFETs.

[BibT_eX]

[DOI]

Harita Sirugudi

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design.

[BibT_eX]

[DOI]

P. Veda Bhanu

Soumya J.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Design of Area Optimised, Energy Efficient Quaternary Circuits Using CNTFETs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2018

Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Energy efficient design of CNFET-based multi-digit ternary adders.

[BibT_eX]

[DOI]

Sai Phaneendra Parlapalli

Microelectron. J., 2018

Design Methodologies for Ternary Logic Circuits.

[BibT_eX]

[DOI]

Sai Phaneendra Parlapalli

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

2017

An ESOP Based Cube Decomposition Technique for Reversible Circuits.

[BibT_eX]

[DOI]

Sai Phaneendra Parlapalli

Proceedings of the Reversible Computation - 9th International Conference, 2017

Optimizing the Reversible Circuits Using Complementary Control Line Transformation.

[BibT_eX]

[DOI]

Proceedings of the Reversible Computation - 9th International Conference, 2017

2016

An Efficient Design Methodology for CNFET Based Ternary Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

2014

An Optimized Design of Reversible Quantum Comparator.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A New Design of an N-Bit Reversible Arithmetic Logic Unit.

[BibT_eX]

[DOI]

Subhankar Pal

Srinivas B. Mandalika

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

2012

Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.

[BibT_eX]

[DOI]

Goutham Makkena

M. Venkata Swamy Nayudu

Proceedings of the 25th International Conference on VLSI Design, 2012

Design of Prefix-Based Optimal Reversible Comparator.

[BibT_eX]

[DOI]

Mandalika B. Srinivas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.

[BibT_eX]

[DOI]

Mandalika B. Srinivas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

CNFET based ternary magnitude comparator.

[BibT_eX]

[DOI]

Phaneendra P. Sai

Proceedings of the International Symposium on Communications and Information Technologies, 2012

2011

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.

[BibT_eX]

[DOI]