Chester Rebeiro

Orcid: 0000-0001-8063-0026

According to our database1, Chester Rebeiro authored at least 79 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
<tt>FortiFix</tt> : A Fault Attack Aware Compiler Framework for Crypto Implementations.
ACM Trans. Design Autom. Electr. Syst., 2024

High Speed High Assurance implementations of Multivariate Quadratic based Signatures.
IACR Cryptol. ePrint Arch., 2024

WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors.
Proceedings of the 33rd USENIX Security Symposium, 2024

2023
Kryptonite: Worst-Case Program Interference Estimation on Multi-Core Embedded Systems.
ACM Trans. Embed. Comput. Syst., October, 2023

SIGNED: A Challenge-Response Scheme for Electronic Hardware Watermarking.
IEEE Trans. Computers, June, 2023

FaultMeter: Quantitative Fault Attack Assessment of Block Cipher Software.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

A Survey of Security Concerns and Countermeasures in Modern Micro-architectures with Transient Execution.
CoRR, 2023

YODA: Covert Communication Channel over Public DNS Resolvers.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Network, 2023

Secure Compiler Framework to Design Fault Attack Resistant Software.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

2022
FadingBF: A Bloom Filter With Consistent Guarantees for Online Applications.
IEEE Trans. Computers, 2022

SUNDEW: An Ensemble of Predictors for Case-Sensitive Detection of Malware.
CoRR, 2022

JUGAAD: Comprehensive Malware Behavior-as-a-Service.
Proceedings of the CSET 2022: Cyber Security Experimentation and Test Workshop, 2022

Privacy-Preserving Decentralized Exchange Marketplaces.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2022

Timed speculative attacks exploiting store-to-load forwarding bypassing cache-based countermeasures.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

RaDaR: A Real-Word Dataset for AI powered Run-time Detection of Cyber-Attacks.
Proceedings of the 31st ACM International Conference on Information & Knowledge Management, 2022

Avatar: Reinforcing Fault Attack Countermeasures in EDA with Fault Transformations.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
FaultDroid: An Algorithmic Approach for Fault-Induced Information Leakage Analysis.
ACM Trans. Design Autom. Electr. Syst., 2021

PERI: A Configurable Posit Enabled RISC-V Core.
ACM Trans. Archit. Code Optim., 2021

A Formal Analysis of Prefetching in Profiled Cache-Timing Attacks on Block Ciphers.
J. Cryptol., 2021

LEASH: Enhancing Micro-architectural Attack Detection with a Reactive Process Scheduler.
CoRR, 2021

2020
ALEXIA: A Processor with Lightweight Extensions for Memory Safety.
ACM Trans. Embed. Comput. Syst., 2020

FEDS: Comprehensive Fault Attack Exploitability Detection for Software Implementations of Block Ciphers.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

SAFARI: Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

ProBLeSS: A Proactive Blockchain Based Spectrum Sharing Protocol Against SSDF Attacks in Cognitive Radio IoBT Networks.
IEEE Netw. Lett., 2020

SIGNED: A Challenge-Response Based Interrogation Scheme for Simultaneous Watermarking and Trojan Detection.
CoRR, 2020

SISSLE in consensus-based Ripple: Some Improvements in Speed, Security, Last Mile Connectivity and Ease of Use.
CoRR, 2020

Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER.
IEEE Comput. Archit. Lett., 2020

PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Spy Cartel: Parallelizing Evict+Time-Based Cache Attacks on Last-Level Caches.
J. Hardw. Syst. Secur., 2019

IPA: an Instruction Profiling-Based Micro-architectural Side-Channel Attack on Block Ciphers.
J. Hardw. Syst. Secur., 2019

Revisiting AES SBox Composite Field Implementations for FPGAs.
IEEE Embed. Syst. Lett., 2019

PERI: A Posit Enabled RISC-V Core.
CoRR, 2019

D-TIME: Distributed Threadless Independent Malware Execution for Runtime Obfuscation.
Proceedings of the 13th USENIX Workshop on Offensive Technologies, 2019

MSMPX: Microarchitectural Extensions for Meltdown Safe Memory Protection.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

SHAKTI-MS: a RISC-V processor for memory safety in C.
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019

Towards Measuring Quality of Service in Untrusted Multi-Vendor Service Function Chains: Balancing Security and Resource Consumption.
Proceedings of the 2019 IEEE Conference on Computer Communications, 2019

Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection.
Proceedings of the International Conference on Computer-Aided Design, 2019

Towards Identifying Early Indicators of a Malware Infection.
Proceedings of the 2019 ACM Asia Conference on Computer and Communications Security, 2019

Formal Verification for Security in IoT Devices.
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019

2018
An Algorithmic Approach to Formally Verify an ECC Library.
ACM Trans. Design Autom. Electr. Syst., 2018

GANDALF: A Fine-Grained Hardware-Software Co-Design for Preventing Memory Attacks.
IEEE Embed. Syst. Lett., 2018

ApproxBC: Blockchain Design Alternatives for Approximation-Tolerant Resource-Constrained Applications.
IEEE Commun. Stand. Mag., 2018

2017
Leakage-Resilient Tweakable Encryption from One-Way Functions.
IACR Cryptol. ePrint Arch., 2017

GANDALF: A fine-grained hardware-software co-design for preventing memory attacks.
CoRR, 2017

Shakti-T: A RISC-V Processor with Light Weight Security Extensions.
Proceedings of the Hardware and Architectural Support for Security and Privacy, 2017

XFC: A Framework for eXploitable Fault Characterization in Block Ciphers.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Template attack on SPA and FA resistant implementation of Montgomery ladder.
IET Inf. Secur., 2016

Accelerating OpenSSL's ECC with low cost reconfigurable hardware.
Proceedings of the International Symposium on Integrated Circuits, 2016

A Formal Security Analysis of Even-Odd Sequential Prefetching in Profiled Cache-Timing Attacks.
Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, 2016

2015
Micro-Architectural Analysis of Time-Driven Cache Attacks: Quest for the Ideal Implementation.
IEEE Trans. Computers, 2015

2014
DRECON: DPA Resistant Encryption by Construction.
Proceedings of the Progress in Cryptology - AFRICACRYPT 2014, 2014

2013
Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Formalizing the Effect of Feistel Cipher Structures on Differential Cache Attacks.
IEEE Trans. Inf. Forensics Secur., 2013

Unraveling timewarp: what all the fuzz is about?
Proceedings of the HASP 2013, 2013

Lightweight cipher implementations on embedded processors.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

PERMS: A Bit Permutation Instruction for Accelerating Software Cryptography.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Boosting Profiled Cache Timing Attacks With A Priori Analysis.
IEEE Trans. Inf. Forensics Secur., 2012

Generalized high speed Itoh-Tsujii multiplicative inversion architecture for FPGAs.
Integr., 2012

Hardware Prefetchers Leak: A Revisit of SVF for Cache-Timing Attacks.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

A Parallel Architecture for Koblitz Curve Scalar Multiplications on FPGA Platforms.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Improved Differential Cache Attacks on SMS4.
Proceedings of the Information Security and Cryptology - 8th International Conference, 2012

Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

2011
Revisiting the Itoh-Tsujii Inversion Algorithm for FPGA Platforms.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Scalar Multiplication on Koblitz Curves using tau<sup>2</sup>-NAF.
IACR Cryptol. ePrint Arch., 2011

A Cache Trace Attack on CAMELLIA.
Proceedings of the Security Aspects in Information Technology, 2011

An Enhanced Differential Cache Attack on CLEFIA for Large Cache Lines.
Proceedings of the Progress in Cryptology - INDOCRYPT 2011, 2011

Accelerating Itoh-Tsujii multiplicative inversion algorithm for FPGAs.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Theoretical modeling of the Itoh-Tsujii Inversion algorithm for enhanced performance on k-LUT based FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2011

Cryptanalysis of CLEFIA Using Differential Methods with Cache Trace Patterns.
Proceedings of the Topics in Cryptology - CT-RSA 2011, 2011

2010
Differential Cache Trace Attack Against CLEFIA.
IACR Cryptol. ePrint Arch., 2010

Pinpointing Cache Timing Attacks on AES.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009
Cache Timing Attacks on Clefia.
Proceedings of the Progress in Cryptology, 2009

2008
Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

High Speed Compact Elliptic Curve Cryptoprocessor for FPGA Platforms.
Proceedings of the Progress in Cryptology, 2008

Theory of Composing Non-linear Machines with Predictable Cyclic Structures.
Proceedings of the Cellular Automata, 2008

2006
Bitslice Implementation of AES.
Proceedings of the Cryptology and Network Security, 5th International Conference, 2006

2005
SCADA with Fault Tolerant CORBA on Fault Tolerant LANE ATM.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005


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