Chester Liu

According to our database, Chester Liu authored at least 13 papers between 2010 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging.

Teyuh Chou, Wei Tang, Mihai D. Rotaru, Chester Liu, Rahul Dutta, Sharon Lim Pei Siang, David Ho Soon Wee, Surya Bhattacharya, Zhengya Zhang

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference.

Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Stephen W. Keckler, Zhengya Zhang

IEEE J. Solid State Circuits, 2021

PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA.

Sung-Gun Cho, Wei Tang, Chester Liu, Zhengya Zhang

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer.

Chester Liu, Jacob Botimer, Zhengya Zhang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2019

A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification.

Thomas Chen, Ching-En Lee, Chester Liu, Zhengya Zhang

IEEE J. Solid State Circuits, 2019

SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS.

Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Stephen W. Keckler, Zhengya Zhang

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018

A 2.56-mm² 718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS.

Chester Liu, Sung-Gun Cho, Zhengya Zhang

IEEE J. Solid State Circuits, 2018

Inference and Learning Hardware Architecture for Neuro- Inspired Sparse Coding Algoerithm.

Chester Liu, Zhengya Zhang

Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017

A 2.56mm² 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS.

Chester Liu, Sung-Gun Cho, Zhengya Zhang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

A 1.40mm² 141mW 898GOPS sparse neuromorphic processor in 40nm CMOS.

Phil Knag, Chester Liu, Zhengya Zhang

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2013

Implementation of a highly scalable blokus duo solver on FPGA.

Chester Liu

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2011

Placement Optimization of Flexible TFT Digital Circuits.

Chester Liu, En-Hua Ma, Wen-En Wei, Chien-Mo James Li, I-Chun Cheng, Yung-Hui Yeh

IEEE Des. Test Comput., 2011

2010

Static timing analysis for flexible TFT circuits.

Chao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li

Proceedings of the 47th Design Automation Conference, 2010