Chessda Uttraphan

According to our database1, Chessda Uttraphan authored at least 2 papers between 2014 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
An optimized buffer insertion algorithm with delay-power constraints for VLSI layouts.
Turkish J. Electr. Eng. Comput. Sci., 2017

2014
An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014


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