Cherry Wakayama
According to our database1,
Cherry Wakayama
authored at least 18 papers
between 2005 and 2024.
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Bibliography
2024
Proceedings of the IEEE Military Communications Conference, 2024
2021
Multi-Fidelity Modeling For The Design Of A Maritime Environmental Survey Network Utilizing Unmanned Underwater Vehicles.
Proceedings of the Winter Simulation Conference, 2021
2015
Utilizing kinematics and selective sweeping in reinforcement learning-based routing algorithms for underwater networks.
Ad Hoc Networks, 2015
Simulation-driven task prioritization using a restless bandit model for active sonar missions.
Proceedings of the 2015 Winter Simulation Conference, 2015
2014
Rollout Algorithms for Data Storage- and Energy-Aware Data Retrieval Using Autonomous Underwater Vehicles.
Proceedings of the International Conference on Underwater Networks & Systems, Rome, Italy, November 12, 2014
2013
Proceedings of the 16th International Conference on Information Fusion, 2013
2012
Linear optimization models with integer solutions for ping control problems in multistatic active acoustic networks.
Proceedings of the 15th International Conference on Information Fusion, 2012
Proceedings of the 15th International Conference on Information Fusion, 2012
Proceedings of the 15th International Conference on Information Fusion, 2012
2011
Forecasting probability of target presence for ping control in multistatic sonar networks using detection and tracking models.
Proceedings of the 14th International Conference on Information Fusion, 2011
Multiple Detection Probabilistic Data Association filter for multistatic target tracking.
Proceedings of the 14th International Conference on Information Fusion, 2011
Proceedings of the 14th International Conference on Information Fusion, 2011
2010
Proceedings of the 13th Conference on Information Fusion, 2010
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits.
Proceedings of the 25th International Conference on Computer Design, 2007
2006
A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005