Cherrice Traver

According to our database1, Cherrice Traver authored at least 11 papers between 1993 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2005
Early evaluation for performance enhancement in phased logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A Coarse-Grain Phased Logic CPU.
IEEE Trans. Computers, 2005

2004
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
A Fine-Grain Phased Logic CPU.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

2002
Generalized Early Evaluation in Self-Timed Circuits.
Proceedings of the 2002 Design, 2002

2001
Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000
The multidisciplinary international virtual design studio (MIVDS).
IEEE Trans. Educ., 2000

1996
Guest Editorial Introduction to the Special Issue on the 1995 IEEE ASIC Conference.
IEEE Trans. Very Large Scale Integr. Syst., 1996

1995
Analyzing and verifying locally clocked circuits with the concurrency workbench.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1993
A Comparison of Synchronous and Asynchronous FSMD Designs.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Rapid-prototyping of high-assurance systems.
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993


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