Cheol Seong Hwang
Orcid: 0000-0002-6254-9758
According to our database1,
Cheol Seong Hwang
authored at least 16 papers
between 2019 and 2023.
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Bibliography
2023
Efficient Method for Error Detection and Correction in In-Memory Computing Based on Reliable Ex-Logic Gates.
Adv. Intell. Syst., May, 2023
2022
Reliable Domain-Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors.
Adv. Intell. Syst., 2022
Training Method for Accurate Off-Chip Training of One-Selector-One-Resistor Crossbar Array with Nonlinearity and Wire Resistance.
Adv. Intell. Syst., 2022
In-Depth Analysis of One Selector-One Resistor Crossbar Array for Its Writing and Reading Operations for Hardware Neural Network with Finite Wire Resistance.
Adv. Intell. Syst., 2022
Memory Window Expansion for Ferroelectric FET based Multilevel NVM: Hybrid Solution with Combination of Polarization and Injected Charges.
Proceedings of the IEEE International Memory Workshop, 2022
2021
<i>InterPhon</i>: <i>Ab initio</i> interface phonon calculations within a 3D electronic structure framework.
Comput. Phys. Commun., 2021
A High-Speed True Random Number Generator Based on a Cu x Te 1- x Diffusive Memristor.
Adv. Intell. Syst., 2021
IEEE Access, 2021
2020
A Stateful Logic Family Based on a New Logic Primitive Circuit Composed of Two Antiparallel Bipolar Memristors.
Adv. Intell. Syst., 2020
Kernel Application of the Stacked Crossbar Array Composed of Self-Rectifying Resistive Switching Memory for Convolutional Neural Networks.
Adv. Intell. Syst., 2020
IEEE Access, 2020
2019
IEEE Access, 2019
IEEE Access, 2019
VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019