Cheol Hong Kim

Orcid: 0000-0003-1837-6631

According to our database1, Cheol Hong Kim authored at least 94 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Integrated beamforming and trajectory optimization algorithm for RIS-assisted UAV system.
ICT Express, 2024

RIS-aided double beamforming optimization algorithm for improving secrecy rate in space-ground integrated networks.
ICT Express, 2024

Deep neural network-based clustering algorithm for multiple flying reconfigurable intelligent surfaces-supported bulk systems.
ICT Express, 2024

Location-based on beam tracking method predicted using GP in UAV-supported systems.
ICT Express, 2024

2023
Correction to: Aggressive GPU cache bypassing with monolithic 3D-based NoC.
J. Supercomput., April, 2023

Aggressive GPU cache bypassing with monolithic 3D-based NoC.
J. Supercomput., March, 2023

Beam Tracking Method Using Unscented Kalman Filter for UAV-Enabled NR MIMO-OFDM System with Hybrid Beamforming.
KSII Trans. Internet Inf. Syst., 2023

2022
Deep Neural Network for Beam and Blockage Prediction in 3GPP-Based Indoor Hotspot Environments.
Wirel. Pers. Commun., 2022

Gearbox Fault Identification Model Using an Adaptive Noise Canceling Technique, Heterogeneous Feature Extraction, and Distance Ratio Principal Component Analysis.
Sensors, 2022

A Method for Pipeline Leak Detection Based on Acoustic Imaging and Deep Learning.
Sensors, 2022

Multitask learning-based secure transmission for reconfigurable intelligent surface-aided wireless communications.
ICT Express, 2022

Online learning-based beam and blockage prediction for indoor millimeter-wave communications.
ICT Express, 2022

Rolling Bearing Fault Diagnosis Based on Improved GAN and 2-D Representation of Acoustic Emission Signals.
IEEE Access, 2022

2021
Construction of a Sensitive and Speed Invariant Gearbox Fault Diagnosis Model Using an Incorporated Utilizing Adaptive Noise Control and a Stacked Sparse Autoencoder-Based Deep Neural Network.
Sensors, 2021

Novel Bearing Fault Diagnosis Using Gaussian Mixture Model-Based Fault Band Selection.
Sensors, 2021

A Novel Hybrid Deep Learning Method for Fault Diagnosis of Rotating Machinery Based on Extended WDCNN and Long Short-Term Memory.
Sensors, 2021

KAWS: Coordinate Kernel-Aware Warp Schedulingand Warp Sharing Mechanism for Advanced GPUs.
J. Inf. Process. Syst., 2021

New Two-Level L1 Data Cache Bypassing Technique for High Performance GPUs.
J. Inf. Process. Syst., 2021

Coordinated Millimeter Wave Beam Selection Using Fingerprint for Cellular-Connected Unmanned Aerial Vehicle.
KSII Trans. Internet Inf. Syst., 2021

Enhancing Matrix Multiplication With a Monolithic 3-D-Based Scratchpad Memory.
IEEE Embed. Syst. Lett., 2021

Efficient Fault Diagnosis of Rolling Bearings Using Neural Network Architecture Search and Sharing Weights.
IEEE Access, 2021

A Novel Framework for Centrifugal Pump Fault Diagnosis by Selecting Fault Characteristic Coefficients of Walsh Transform and Cosine Linear Discriminant Analysis.
IEEE Access, 2021

2020
A novel warp scheduling scheme considering long-latency operations for high-performance GPUs.
J. Supercomput., 2020

Deep Learning-Based Bearing Fault Diagnosis Method for Embedded Systems.
Sensors, 2020

2019
Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018
Application Characteristics-Aware Sporadic Cache Bypassing for high performance GPGPUs.
J. Parallel Distributed Comput., 2018

Dynamic Selective Warp Scheduling for GPUs Using L1 Data Cache Locality Information.
Proceedings of the Parallel and Distributed Computing, 2018

A Study on L1 Data Cache Bypassing Methods for High-Performance GPUs.
Proceedings of the Parallel and Distributed Computing, 2018

Memory Contention Aware Power Management for High Performance GPUs.
Proceedings of the Parallel and Distributed Computing, 2018

2017
Early miss prediction based periodic cache bypassing for high performance GPUs.
Microprocess. Microsystems, 2017

A dynamic CTA scheduling scheme for massive parallel computing.
Clust. Comput., 2017

An FPGA-Based Implementation of a Pipelined FFT Processor for High-Speed Signal Processing Applications.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
NTB branch predictor: dynamic branch predictor for high-performance embedded processors.
J. Supercomput., 2016

Accelerating IP routing algorithm using graphics processing unit for high speed multimedia communication.
Multim. Tools Appl., 2016

Accelerating Envelope Analysis-Based Fault Diagnosis Using a General-Purpose Graphics Processing Unit.
Proceedings of the Integrated Uncertainty in Knowledge Modelling and Decision Making, 2016

Multi-core Accelerated Discriminant Feature Selection for Real-Time Bearing Fault Diagnosis.
Proceedings of the Trends in Applied Knowledge-Based Systems and Data Science, 2016

2015
An optimal many-core model-based supercomputing for accelerating video-equipped fire detection.
J. Supercomput., 2015

A fast and energy-efficient Hamming decoder for software-defined radio using graphics processing units.
J. Supercomput., 2015

A Service-oriented DDoS detection mechanism using pseudo state in a flow router.
Multim. Tools Appl., 2015

A new cache replacement algorithm for last-level caches by exploiting tag-distance correlation of cache lines.
Microprocess. Microsystems, 2015

Computationally efficient implementation of a Hamming code decoder using graphics processing unit.
J. Commun. Networks, 2015

A GPU-based (8, 4) Hamming decoder for secure transmission of watermarked medical images.
Clust. Comput., 2015

A novel memory management technique for cloud client devices.
Clust. Comput., 2015

A semantic hot replication of self organization software platform Router.
Proceedings of the 9th IEEE International Conference on Semantic Computing, 2015

2014
Concurrent warp execution: improving performance of GPU-likely SIMD architecture by increasing resource utilization.
J. Supercomput., 2014

Measuring Variance between Smartphone Energy Consumption and Battery Life.
Computer, 2014

Analysis on the Power Efficiency of Mobile Systems Varying Device Parameters.
Proceedings of the 2014 International Conference on IT Convergence and Security, 2014

Impact of Clock Frequency and Number of Cores on GPU Performance.
Proceedings of the 2014 International Conference on IT Convergence and Security, 2014

A Novel Prefetch Technique for High Performance Embedded System.
Proceedings of the 2014 International Conference on IT Convergence and Security, 2014

Novel MCS Based Relay Protocols for Throughput Optimization Using AMC in LTE-Advanced System.
Proceedings of the 47th Hawaii International Conference on System Sciences, 2014

2013
An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture.
Wirel. Pers. Commun., 2013

An efficient scheduling scheme using estimated execution time for heterogeneous computing systems.
J. Supercomput., 2013

Highly reliable state monitoring system for induction motors using dominant features in a two-dimension vibration signal.
New Rev. Hypermedia Multim., 2013

Design space exploration in many-core processors for sound synthesis of plucked string instruments.
J. Parallel Distributed Comput., 2013

High-Performance Sound Engine of Guitar on Optimal Many-Core Processors.
Proceedings of the Mobile, Ubiquitous, and Intelligent Computing, 2013

Analysis of Memory Management Policies for Heterogeneous Cloud Computing.
Proceedings of the International Conference on Information Science and Applications, 2013

A Residual Power Balancing Routing by Traffic-Splitting Transmission in Mobile Ad-Hoc Networks.
Proceedings of the International Conference on Information Science and Applications, 2013

Precoding optimization for Interference Cancellation in multiuser relay networks for LTE-advanced.
Proceedings of the 10th IEEE Consumer Communications and Networking Conference, 2013

2012
Performance Analysis of New SNR Estimation Methodology based on Preamble Approach.
Proceedings of the SIGMAP and WINSYS 2012, 2012

Novel Channel Estimation Algorithm using Various Filter Design in LTE-Advanced System.
Proceedings of the SIGMAP and WINSYS 2012, 2012

Sphere Decoding Complexity Reduction using an Adaptive SD-OSIC Algorithm.
Proceedings of the SIGMAP and WINSYS 2012, 2012

Adaptive Dynamic Frequency Scaling for Thermal-Aware 3D Multi-core Processors.
Proceedings of the Computational Science and Its Applications - ICCSA 2012, 2012

2011
Exploration of CPU/GPU co-execution: from the perspective of performance, energy, and temperature.
Proceedings of the Research in Applied Computation Symposium, 2011

Audio Segmentation and Classification Using a Temporally Weighted Fuzzy C-Means Algorithm.
Proceedings of the Advances in Neural Networks - ISNN 2011, 2011

Implementation of High-Performance Sound Synthesis Engine for Plucked-String Instruments.
Proceedings of the Advanced Intelligent Computing - 7th International Conference, 2011

Thermal-Aware Floorplan Schemes for Reliable 3D Multi-core Processors.
Proceedings of the Computational Science and Its Applications - ICCSA 2011, 2011

Complexity Adaptive Branch Predictor for Thermal-Aware 3D Multi-core Processors.
Proceedings of the Control and Automation, and Energy System Engineering, 2011

2010
Energy-aware instruction cache design using small trace cache.
IET Comput. Digit. Tech., 2010

An Efficient Audio Watermarking Algorithm in Frequency Domain for Copyright Protection.
Proceedings of the Security Technology, Disaster Recovery and Business Continuity, 2010

Robust Audio Watermarking Scheme Based on Deterministic Plus Stochastic Model.
Proceedings of the Security Technology, Disaster Recovery and Business Continuity, 2010

Energy-aware Filter Cache Architecture for Multicore Processors.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Performance Evaluation of Multimedia Extensions on Variable Many-Core Processors.
Proceedings of the 2010 International Conference on Computer Design, 2010

Thermal-aware Duplicated Filter Cache for Improving Processor Reliability.
Proceedings of the 2010 International Conference on Computer Design, 2010

Thermal Analysis for 3D Multi-core Processors with Dynamic Frequency Scaling.
Proceedings of the 9th IEEE/ACIS International Conference on Computer and Information Science, 2010

2009
Parallel Approach to Fuzzy Vector Quantization for Image Compression.
Proceedings of the 10th ACIS International Conference on Software Engineering, 2009

Throughput Improvement of Iterative Decoding Algorithm in the V-BLAST-AMC System with a STD Scheme.
Proceedings of the 2009 International Conference on Wireless Networks, 2009

Performance Analysis of the Combined AMC-MIMO Systems with Independent MCS Level Selection.
Proceedings of the 2009 International Conference on Wireless Networks, 2009

The impact of liquid cooling on 3D multi-core processors.
Proceedings of the 27th International Conference on Computer Design, 2009

2008
An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Improvement of Iterative Decoding Algorithm in the Adaptive Modulation and Coding System.
Proceedings of the 5th IEEE Consumer Communications and Networking Conference, 2008

Energy-Effective Instruction Fetch Unit for Embedded Processors.
Proceedings of the 5th IEEE Consumer Communications and Networking Conference, 2008

Design of New Closed-Loop Spatial Multiplexing Scheme Using Linear Precoder.
Proceedings of the 5th IEEE Consumer Communications and Networking Conference, 2008

Loop Detection for Energy-Aware High Performance Embedded Processors.
Proceedings of the 3rd IEEE Asia-Pacific Services Computing Conference, 2008

2007
Is the Complicated ECC Array Necessary for Data Caches?
Proceedings of the 2007 International Conference on Computer Design, 2007

2006
PP-cache: A partitioned power-aware instruction cache architecture.
Microprocess. Microsystems, 2006

Advanced High-Level Cache Management by Processor Access Information.
J. Inf. Sci. Eng., 2006

An Energy-Efficient Partitioned Instruction Cache Architecture for Embedded Processors.
IEICE Trans. Inf. Syst., 2006

2005
Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic.
Proceedings of the Embedded Computer Systems: Architectures, 2005

First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption.
Proceedings of the Embedded Computer Systems: Architectures, 2005

An Effective Instruction Cache Prefetch Policy by Exploiting Cache History Information.
Proceedings of the Embedded and Ubiquitous Computing, 2005

2004
Level 1 & Victim Cache Management with Processor Reuse Information.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

A Novel Approach to Improve Cache Performance in Ring-Based Multiprocessors.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

Hybrid Technique for Reducing Energy Consumption in High Performance Embedded Processor.
Proceedings of the Embedded and Ubiquitous Computing, 2004

Adaptive Block Management for Victim Cache by Exploiting L1 Cache History Information.
Proceedings of the Embedded and Ubiquitous Computing, 2004


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