Chenyun Pan

According to our database, Chenyun Pan authored at least 28 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus.

Zhenlin Pei, Hsiao-Hsuan Liu, Mahta Mayahinia, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Dawit Burusie Abdi, James Myers, Chenyun Pan

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024

QPUF 2.0: Exploring Quantum Physical Unclonable Functions for Security-by-Design of Energy Cyber-Physical Systems.

Venkata K. V. V. Bathalapalli, Saraju P. Mohanty, Chenyun Pan, Elias Kougianos

CoRR, 2024

A Novel Delay-Aware Packing Algorithm for FPGA Architecture Using RFET.

Sheng Lu, Liuting Shang, Sungyong Jung, Yichen Zhang, Chenyun Pan

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Emerging Reconfigurable Logic Device Based FPGA Design and Optimization.

Sheng Lu, Liuting Shang, Sungyong Jung, Chenyun Pan

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023

Deep learning in physical layer communications: Evolution and prospects in 5G and 6G networks.

Chengchen Mao, Zongwen Mu, Qilian Liang, Ioannis D. Schizas, Chenyun Pan

IET Commun., October, 2023

Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis.

Liuting Shang, Azad Naeemi, Chenyun Pan

IEEE Open J. Comput. Soc., 2023

A statistical approach for neural network pruning with application to internet of things.

Chengchen Mao, Qilian Liang, Chenyun Pan, Ioannis D. Schizas

EURASIP J. Wirel. Commun. Netw., 2023

Novel Fence Generation Methods for Accelerating Reconfigurable Exact Synthesis.

Liuting Shang, Sheng Lu, Sungyong Jung, Chenyun Pan

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A Technology/Circuit Co-design Framework for Emerging Reconfigurable Devices.

Sheng Lu, Zhenlin Pei, Liuting Shang, Sungyong Jung, Chenyun Pan

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access.

Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Shairfe Muhammad Salahuddin, Francky Catthoor, Zsolt Tokei, Chenyun Pan

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

QPUF: Quantum Physical Unclonable Functions for Security-by-Design of Industrial Internet-of-Things.

Venkata K. V. V. Bathalapalli, Saraju P. Mohanty, Chenyun Pan, Elias Kougianos

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect.

Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Chenyun Pan

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2020

Fast Linear Programming Optimization Using Crossbar-Based Analog Accelerator.

Liuting Shang, Muhammad Adil, Ramtin Madani, Chenyun Pan

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2019

A Mixed Signal Architecture for Convolutional Neural Networks.

Qiuwen Lou, Chenyun Pan, John McGuinness, András Horváth, Azad Naeemi, Michael T. Niemier, Xiaobo Sharon Hu

ACM J. Emerg. Technol. Comput. Syst., 2019

2018

Generic system-level modeling and optimization for beyond CMOS device applications.

Victor Huang, Chenyun Pan, Azad Naeemi

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

2017

Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications.

Chenyun Pan, Azad Naeemi

CoRR, 2017

Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions.

Chenyun Pan, Azad Naeemi

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices.

Chenyun Pan, Azad Naeemi

CoRR, 2016

Impact of interconnect variability on circuit performance in advanced technology nodes.

Divya Prasad, Chenyun Pan, Azad Naeemi

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Performance modeling and optimization for on-chip interconnects in 3D memory arrays.

Javaneh Mohseni, Chenyun Pan, Azad Naeemi

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Device/system performance modeling of stacked lateral NWFET logic.

Victor Huang, Chenyun Pan, Dmitry Yakimets, Praveen Raghavan, Azad Naeemi

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015

A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies.

Chenyun Pan, Azad Naeemi

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node.

Chenyun Pan, Praveen Raghavan, Francky Catthoor, Zsolt Tokei, Azad Naeemi

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014

An analytical approach to system-level variation analysis and optimization for multi-core processor.

Chenyun Pan, Saibal Mukhopadhyay, Azad Naeemi

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

BEOL Scaling Limits and Next Generation Technology Prospects.

Azad Naeemi, Ahmet Ceyhan, Vachan Kumar, Chenyun Pan, Rouhollah M. Iraei, Shaloo Rakheja

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs.

Chenyun Pan, Ahmet Ceyhan, Azad Naeemi

Proceedings of the International Symposium on Quality Electronic Design, 2013

2012

Device- and system-level performance modeling for graphene P-N junction logic.

Chenyun Pan, Azad Naeemi

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model.

Chenyun Pan, Azad Naeemi

Proceedings of the IEEE International Conference on IC Design & Technology, 2012