Chenle Yu

According to our database, Chenle Yu authored at least 7 papers between 2020 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

HiPART: High-Performance Technology for Advanced Real-Time Systems.

Sara Royuela, Adrian Munera, Chenle Yu, Josep Pinot

Proceedings of the 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2025

2024

Event-Based OpenMP Tasks for Time-Sensitive GPU-Accelerated Systems.

Cyril Cetre, Chenle Yu, Sara Royuela, Rémi Barrere, Eduardo Quiñones, Damien Gratadour

Proceedings of the Advancing OpenMP for Future Accelerators, 2024

Enhancing Heterogeneous Computing Through OpenMP and GPU Graph.

Chenle Yu, Sara Royuela, Eduardo Quiñones

Proceedings of the 53rd International Conference on Parallel Processing, 2024

2023

Taskgraph: A Low Contention OpenMP Tasking Framework.

Chenle Yu, Sara Royuela, Eduardo Quiñones

IEEE Trans. Parallel Distributed Syst., August, 2023

2021

Enhancing OpenMP Tasking Model: Performance and Portability.

Chenle Yu, Sara Royuela, Eduardo Quiñones

Proceedings of the OpenMP: Enabling Massive Node-Level Parallelism, 2021

A Low Overhead Tasking Model for OpenMP.

Chenle Yu, Sara Royuela, Eduardo Quiñones

Proceedings of the Euro-Par 2021: Parallel Processing Workshops, 2021

2020

OpenMP to CUDA graphs: a compiler-based transformation to enhance the programmability of NVIDIA devices.

Chenle Yu, Sara Royuela, Eduardo Quiñones

Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020