Chengyu Huang

According to our database, Chengyu Huang authored at least 6 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS.

Chengyu Huang, Kezhuo Ma, Sihao Chen, Jiaxuan Fan, Nan Sun, Huazhong Yang, Xueqing Li

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging.

Yushen Fu, Chengyu Huang, Longqiang Lai, Nan Sun, Xueqing Li, Huazhong Yang

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration.

Yushen Fu, Chengyu Huang, Limeng Sun, Weiguang Meng, Xueqing Li, Huazhong Yang

IEEE Trans. Very Large Scale Integr. Syst., February, 2023

2021

Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-Steering DACs.

Yang Liu, Yushen Fu, Chengyu Huang, Huazhong Yang, Xueqing Li

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching.

Chengyu Huang, Yushen Fu, Zekun Yang, Yang Liu, Nan Sun, Xueqing Li, Huazhong Yang

Proceedings of the 47th ESSCIRC 2021, 2021

2020

AutoShrink: A Topology-Aware NAS for Discovering Efficient Neural Architecture.

Tunhou Zhang, Hsin-Pai Cheng, Zhenwen Li, Feng Yan, Chengyu Huang, Hai Helen Li, Yiran Chen

Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020