Chengyu Huang

Orcid: 0009-0007-9829-7883

Affiliations:
  • Tsinghua University, Department of Electronic Engineering, Beijing, China


According to our database1, Chengyu Huang authored at least 7 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2025
A 28-nm 8-Bit 16-GS/ DAC With >60 dBc/>40 dBc SFDR Up To 2.3 GHz/5.4 GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2025

2024
A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023

2021
Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-Steering DACs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching.
Proceedings of the 47th ESSCIRC 2021, 2021

2020
AutoShrink: A Topology-Aware NAS for Discovering Efficient Neural Architecture.
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020


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