Chengshuo Yu
Orcid: 0000-0003-0897-7871
According to our database1,
Chengshuo Yu
authored at least 16 papers
between 2020 and 2024.
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Bibliography
2024
A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024
A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations.
IEEE J. Solid State Circuits, August, 2024
CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully Parallel Spin Updates and Equalization of Spin States.
IEEE J. Solid State Circuits, January, 2024
2023
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array.
IEEE J. Solid State Circuits, 2023
A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks.
IEEE J. Solid State Circuits, 2022
An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks.
Proceedings of the International SoC Design Conference, 2020
A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020