Chengning Wang
Orcid: 0000-0002-7551-5610
According to our database1,
Chengning Wang
authored at least 19 papers
between 2017 and 2024.
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Bibliography
2024
STAGGER: Enabling All-in-One Subarray Sensing for Efficient Module-level Processing in Open-Bitline ReRAM.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
ICON: An IR Drop Compensation Method at OU Granularity with Low Overhead for eNVM-based Accelerators.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Improving Write Performance on Cross-Point RRAM Arrays by Leveraging Multidimensional Non-Uniformity of Cell Effective Voltage.
IEEE Trans. Computers, 2021
EnTiered-ReRAM: An Enhanced Low Latency and Energy Efficient TLC Crossbar ReRAM Architecture.
IEEE Access, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
CCHL: Compression-Consolidation Hardware Logging for Efficient Failure-Atomic Persistent Memory Updates.
Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020
2019
ACM Trans. Design Autom. Electr. Syst., 2019
Proceedings of the 35th Symposium on Mass Storage Systems and Technologies, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
2018
CACF: A Novel Circuit Architecture Co-optimization Framework for Improving Performance, Reliability and Energy of ReRAM-based Main Memory System.
ACM Trans. Archit. Code Optim., 2018
Asymmetric-ReRAM: A Low Latency and High Reliability Crossbar Resistive Memory Architecture.
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
2017
DAWS: Exploiting Crossbar Characteristics for Improving Write Performance of High Density Resistive Memory.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017