Chengmo Yang
Orcid: 0000-0003-0978-1504
According to our database1,
Chengmo Yang
authored at least 97 papers
between 2006 and 2024.
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Bibliography
2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
Proceedings of the 32nd USENIX Security Symposium, 2023
FHE-Booster: Accelerating Fully Homomorphic Execution with Fine-tuned Bootstrapping Scheduling.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023
2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Behavioral Synthesis for Hardware Security, 2022
2021
Tolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight Approximation.
ACM Trans. Embed. Comput. Syst., 2021
DEPS: Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Charger-Surfing: Exploiting a Power Line Side-Channel for Smartphone Information Leakage.
Proceedings of the 30th USENIX Security Symposium, 2021
Safeguarding the Intelligence of Neural Networks with Built-in Light-weight Integrity MArks (LIMA).
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
A Self-Test Framework for Detecting Fault-induced Accuracy Drop in Neural Network Accelerators.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
IEEE Trans. Emerg. Top. Comput., 2020
Low Overhead Online Data Flow Tracking for Intermittently Powered Non-Volatile FPGAs.
ACM J. Emerg. Technol. Comput. Syst., 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Monitoring the Health of Emerging Neural Network Accelerators with Cost-effective Concurrent Test.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Comprehensive Evaluation of Program Reliability with ComFIDet: An Integrated Fault Injection and Detection Framework for Embedded Systems.
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Proceedings of the IEEE International Conference on Acoustics, 2019
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
A Processing-In-Memory Implementation of SHA-3 Using a Voltage-Gated Spin Hall-Effect Driven MTJ-based Crossbar.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Compiler-Directed and Architecture-Independent Mitigation of Read Disturbance Errors in STT-RAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Embed. Syst. Lett., 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Lowering the barrier to online malware detection through low frequency sampling of HPCs.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
FastGC: accelerate garbage collection via an efficient copyback-based data migration in SSDs.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
VLSI Design, 2017
ACM Trans. Embed. Comput. Syst., 2017
ACM Trans. Embed. Comput. Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Segment and Conflict Aware Page Allocation and Migration in DRAM-PCM Hybrid Main Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proc. Priv. Enhancing Technol., 2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Improving read performance via selective Vpass reduction on high density 3D NAND flash memory.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017
CooECC: A Cooperative Error Correction Scheme to Reduce LDPC Decoding Latency in NAND Flash.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Leveraging access port positions to accelerate page table walk in DWM-based main memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
Fully Exploiting PCM Write Capacity Within Near Zero Cost Through Segment-Based Page Allocation.
ACM J. Emerg. Technol. Comput. Syst., 2016
Towards a Scalable and Write-Free Multi-version Checkpointing Scheme in Solid State Drives.
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Qualifying non-volatile register files for embedded systems through compiler-directed write minimization and balancing.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Non-volatile memories in FPGAs: Exploiting logic similarity to accelerate reconfiguration and increase programming cycles.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Secure and Durable (SEDURA): An Integrated Encryption and Wear-leveling Framework for PCM-based Main Memory.
Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Nonvolatile main memory aware garbage collection in high-level language virtual machine.
Proceedings of the 2015 International Conference on Embedded Software, 2015
Improving MPSoC reliability through adapting runtime task schedule based on time-correlated fault behavior.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Improving performance and lifetime of DRAM-PCM hybrid main memory through a proactive page allocation strategy.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Guiding fault-driven adaption in multicore systems through a reliability-aware static task schedule.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling.
IEEE Trans. Emerg. Top. Comput., 2014
Prolonging PCM lifetime through energy-efficient, segment-aware, and wear-resistant page allocation.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memory.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Improving multilevel PCM reliability through age-aware reading and writing strategies.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Exploiting heterogeneity in MPSoCs to prevent potential trojan propagation across malicious IPs.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
3M-PCM: Exploiting multiple write modes MLC phase change main memory in embedded systems.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
Leveraging microarchitectural side channel information to efficiently enhance program control flow integrity.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
2013
Boosting efficiency of fault detection and recovery throughapplication-specific comparison and checkpointing.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2013
Fault detection and recovery efficiency co-optimization through compile-time analysis and runtime adaptation.
Proceedings of the International Conference on Compilers, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Full Fault Resilience and Relaxed Synchronization Requirements at the Cache-Memory Interface.
IEEE Trans. Very Large Scale Integr. Syst., 2011
J. Parallel Distributed Comput., 2011
Computer, 2011
Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache.
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011
Proceedings of the 11th International Conference on Embedded Software, 2011
Frugal but flexible multicore topologies in support of resource variation-driven adaptivity.
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Tackling computation uncertainty through fine-grained and predictable execution adaptivity in multicore systems.
PhD thesis, 2010
Des. Autom. Embed. Syst., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurations.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
2009
Processor reliability enhancement through compiler-directed register file peak temperature reduction.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009
Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude.
Proceedings of the Design, Automation and Test in Europe, 2009
Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization.
Proceedings of the 2008 International Conference on Compilers, 2008
2007
Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs.
Proceedings of the 2007 International Conference on Compilers, 2007
2006
Proceedings of the 2006 International Conference on Compilers, 2006
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006