Chenglong Zou

According to our database, Chenglong Zou authored at least 21 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

BrainQN: Enhancing the Robustness of Deep Reinforcement Learning with Spiking Neural Networks.

Shuo Feng, Jian Cao, Zehong Ou, Guang Chen, Yi Zhong, Zilin Wang, Juntong Yan, Jue Chen, Bingsen Wang, Chenglong Zou, Zebang Feng, Yuan Wang

Adv. Intell. Syst., September, 2024

How the Brain Achieves Real-Time Vision: A Spiking Position Perception Model.

Kefei Liu, Jingjie Shang, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Kanglin Xiao, Yi Zhong, Yuan Wang

IEEE Trans. Cogn. Dev. Syst., June, 2024

HPGA: An Improved Hybrid Genetic Algorithm with Parallel Acceleration for Dynamic Flexible Job-shop Scheduling Problem.

Chenglong Zou, Zhenqi Huang, Xiulei Qin, Yonggui Huang, Yunhuai Liu

Proceedings of the 7th International Conference on Big Data Technologies, 2024

2023

Toward a Lossless Conversion for Spiking Neural Networks with Negative-Spike Dynamics.

Chenglong Zou, Xiaoxin Cui, Guang Chen, Yuanyuan Jiang, Yuan Wang

Adv. Intell. Syst., December, 2023

Real-Time Target Tracking System With Spiking Neural Networks Implemented on Neuromorphic Chips.

Kefei Liu, Xiaoxin Cui, Xiang Ji, Yisong Kuang, Chenglong Zou, Yi Zhong, Kanglin Xiao, Yuan Wang

IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

2022

ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator.

Yisong Kuang, Xiaoxin Cui, Zilin Wang, Chenglong Zou, Yi Zhong, Kefei Liu, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang

IEEE Trans. Very Large Scale Integr. Syst., 2022

Modular building blocks for mapping spiking neural networks onto a programmable neuromorphic processor.

Chenglong Zou, Xiaoxin Cui, Guang Chen, Shuo Feng, Kefei Liu, Xinan Wang, Yuan Wang

Microelectron. J., 2022

An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight.

Yisong Kuang, Xiaoxin Cui, Chenglong Zou, Yi Zhong, Zhenhui Dai, Zilin Wang, Kefei Liu, Dunshan Yu, Yuan Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Hybrid Spiking Recurrent Neural Network on Hardware for Efficient Emotion Recognition.

Chenglong Zou, Xiaoxin Cui, Yisong Kuang, Yuan Wang, Xinan Wang

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

A Full-Neuron Memory Model Designed for Neuromorphic Systems.

Kefei Liu, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Yi Zhong, Kanglin Xiao, Yuan Wang

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS.

Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Yuan Wang, Dunshan Yu, Ru Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2021

28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance.

Qingyun Zou, Xiaoxin Cui, Zhenhui Dai, Yisong Kuang, Yi Zhong, Chenglong Zou, Xiaole Cui

IEICE Electron. Express, 2021

A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations.

Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

A Novel Conversion Method for Spiking Neural Network using Median Quantization.

Chenglong Zou, Xiaoxin Cui, Jiexian Ge, Hanghang Ma, Xin'an Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Deep Spiking Convolutional Neural Networks for Programmable Neuro-synaptic System.

Chenglong Zou, Xin'an Wang, Boxing Xu, Yisong Kuang, Xiaoxin Cui

Proceedings of the 13th IEEE International Conference on ASIC, 2019

BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware Overhead.

Jiexian Ge, Xiaoxin Cui, Kanglin Xiao, Chenglong Zou, Yi-Hsiang Chen, Rongshan Wei

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

BenchBox: A User-Driven Benchmarking Framework for Fat-Client Storage Systems.

Raúl Gracia Tinedo, Chenglong Zou, Marc Sánchez Artigas, Pedro García López

IEEE Trans. Parallel Distributed Syst., 2018

2017

COSY: An Energy-Efficient Hardware Architecture for Deep Convolutional Neural Networks Based on Systolic Array.

Chen Xin, Qiang Chen, Miren Tian, Mohan Ji, Chenglong Zou, Xin'an Wang, Bo Wang

Proceedings of the 23rd IEEE International Conference on Parallel and Distributed Systems, 2017

A low bit-width parameter representation method for hardware-oriented convolution neural networks.

Qiang Chen, Chen Xin, Chenglong Zou, Xin'an Wang, Bo Wang

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2014

Quotient Complexity of Closed Languages.

Janusz A. Brzozowski, Galina Jirásková, Chenglong Zou

Theory Comput. Syst., 2014

2012

On orienting graphs for connectivity: Projective planes and Halin graphs.

Joseph Cheriyan, Chenglong Zou

Oper. Res. Lett., 2012