Chengjun Wu
Orcid: 0000-0001-8512-9783
According to our database1,
Chengjun Wu
authored at least 10 papers
between 2015 and 2024.
Collaborative distances:
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Bibliography
2024
DSC-TRCP: Dynamically Self-Calibrating Tunable Replica Critical Paths Based Timing Monitoring for Variation Resilient Circuits.
IEEE J. Solid State Circuits, July, 2024
2023
Microarmature Solder Surface Detection: An Adaptive Central Region Sample Selection Anchor Free Framework.
IEEE Trans. Instrum. Meas., 2023
2021
A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS.
IEEE J. Solid State Circuits, 2021
Energy-Efficient Design of Large Fan-in Dynamic One-hot Multiplexer in 28nm CMOS Technology.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS.
IEEE Trans. Circuits Syst., 2020
2019
ynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
2015
Quantum Inf. Comput., 2015