Chenghua Wang

Jiajie Xu

Future Gener. Comput. Syst., December, 2023

Design of High Hardware Efficiency Approximate Floating-Point FFT Processor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

High-Throughput Polynomial Multiplier for Accelerating Saber on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

ENAP: An Efficient Number-Aware Pruning Framework for Design Space Exploration of Approximate Configurations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

Probability density function based data augmentation for deep neural network automatic modulation classification with limited training data.

[BibT_eX]

[DOI]

IET Commun., April, 2023

Security and Approximation: Vulnerabilities in Approximation-Aware Testing.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2023

An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A Novel Method Against Hardware Trojans in Approximate Circuits.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Novel Intrinsic Physical Unclonable Function Design for Post-quantum Cryptography.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

An EEG annotation system facilitating brain disease research.

[BibT_eX]

[DOI]

Proceedings of the 16th International Congress on Image and Signal Processing, 2023

Automated data set construction system for clinical EEG research.

[BibT_eX]

[DOI]

Proceedings of the 16th International Congress on Image and Signal Processing, 2023

An Energy-efficient Approximate DCT Design for Image Processing (Invited).

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

An Efficient Hardware Accelerator of High-Speed NTT for CRYSTALS-Kyber Post-Quantum Cryptography.

[BibT_eX]

[DOI]

Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

2022

Deep Learning Based Low Complexity Symbol Detection and Modulation Classification Detector.

[BibT_eX]

[DOI]

IEICE Trans. Commun., August, 2022

A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

AxRMs: Approximate Recursive Multipliers Using High-Performance Building Blocks.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

A Dynamically Configurable PUF and Dynamic Matching Authentication Protocol.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Design of Unsigned Approximate Hybrid Dividers Based on Restoring Array and Logarithmic Dividers.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications.

[BibT_eX]

[DOI]

IEEE Internet Things J., 2022

TCAD Simulation of Single Event Transient in Si Bulk MOSFET at Cryogenic Temperature.

[BibT_eX]

[DOI]

Tongshan Lu

IEEE Access, 2022

A Novel Combined Correlation Power Analysis (CPA) Attack on Schoolbook Polynomial Multiplication in Lattice-based Cryptosystems.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

Architectural-Space Exploration of Energy-Efficient Approximate Arithmetic Units for Error-Tolerant Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Horizontal Correlation Analysis without Precise Location on Schoolbook Polynomial Multiplication of Lattice-based Cryptosystem.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

PAxC: A Probabilistic-oriented Approximate Computing Methodology for ANNs.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Recognizing the consciousness states of DOC patients by classifying EEG signal.

[BibT_eX]

[DOI]

Proceedings of the 15th International Congress on Image and Signal Processing, 2022

A2TN: Aesthetic-Based Adversarial Transfer Network for Cross-Domain Recommendation.

[BibT_eX]

[DOI]

Yu Sang

Proceedings of the Web and Big Data - 6th International Joint Conference, 2022

Design of Approximate Floating-point FFT with Mantissa Bit-width Adjustment Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

Lightweight and Efficient Hardware Implementation for Saber Using NTT Multiplication.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

An Automated Logic-Level Framework for Approximate Modular Arithmetic Circuits.

[BibT_eX]

[DOI]

Proceedings of the Approximate Computing, 2022

2021

AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2021

Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning.

[BibT_eX]

[DOI]

IEEE Trans. Sustain. Comput., 2021

AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

An Energy Efficient Accelerator for Bidirectional Recurrent Neural Networks (BiRNNs) Using Hybrid-Iterative Compression With Error Sensitivity.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Analog Circuit Soft Fault Diagnosis Based on Sparse Random Projections and K-Nearest Neighbor.

[BibT_eX]

[DOI]

Jian Sun

Guobin Hu

Sci. Program., 2021

A Hardware/Software Co-Design Methodology for Adaptive Approximate Computing in clustering and ANN Learning.

[BibT_eX]

[DOI]

IEEE Open J. Comput. Soc., 2021

A lightweight key renewal scheme based authentication protocol with configurable RO PUF for clustered sensor networks.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Dynamically Configurable Physical Unclonable Function based on RRAM Crossbar.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

A Dynamic Highly Reliable SRAM-Based PUF Retaining Memory Function.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Towards CRYSTALS-Kyber: A M-LWE Cryptoprocessor with Area-Time Trade-Off.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 10-b 500MS/s Partially Loop-Unrolled SAR ADC with a Comparator Offset Calibration Technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

An Efficient and Parallel R-LWE Cryptoprocessor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Hybrid Low Radix Encoding-Based Approximate Booth Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Transformer PUF : A Highly Flexible Configurable RO PUF Based on FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

DC-LSTM: Deep Compressed LSTM with Low Bit-Width and Structured Matrices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

AxMM: Area and Power Efficient Approximate Modular Multiplier for R-LWE Cryptosystem.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Programmable Ring Oscillator PUF Based on Switch Matrix.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Security Analysis of Hardware Trojans on Approximate Circuits.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2019

Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Design and Analysis of Approximate Redundant Binary Multipliers.

[BibT_eX]

[DOI]

Earl E. Swartzlander Jr.

Fabrizio Lombardi

IEEE Trans. Computers, 2019

High-performance approximate half and full adder cells using NAND logic gate.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Theoretical Analysis of Configurable RO PUFs and Strategies to Enhance Security.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Dynamic Reconfigurable PUFs Based on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Theoretical Analysis of Delay-Based PUFs and Design Strategies for Improvement.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications.

[BibT_eX]

[DOI]

Peipei Yin

Earl E. Swartzlander Jr.

Fabrizio Lombardi

J. Signal Process. Syst., 2018

Data Compression Device Based on Modified LZ4 Algorithm.

[BibT_eX]

[DOI]

Earl E. Swartzlander Jr.

IEEE Trans. Consumer Electron., 2018

Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design.

[BibT_eX]

[DOI]

IEEE Access, 2018

A Highly Flexible Lightweight and High Speed True Random Number Generator on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Hardware/Software Co-design Method for Approximate Semi-Supervised K-Means Clustering.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Design of Approximate FFT with Bit-width Selection Algorithms.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design Exploration of Small Bit-Width Multipliers Using Approximate Logic Design (ALD) Tool.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Design of Dynamic Range Approximate Logarithmic Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A machine learning attack resistant multi-PUF design on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Combining Restoring Array and Logarithmic Dividers into an Approximate Hybrid Design.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

Attacking Arbiter PUFs Using Various Modeling Attack Algorithms: A Comparative Study.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

XOR gate based low-cost configurable RO PUF.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Design and Analysis of Inexact Floating-Point Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

A Reconfigurable Memory PUF Based on Tristate Inverter Arrays.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Design of approximate Redundant Binary multipliers.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Design and Performance Evaluation of Approximate Floating-Point Multipliers.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Design and evaluation of an approximate Wallace-Booth multiplier.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Low-cost configurable ring oscillator PUF with improved uniqueness.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Live demonstration: An automatic evaluation platform for physical unclonable function test.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Reduced-Dimensional PARAFAC-Based Algorithm for Joint Angle and Doppler Frequency Estimation in Monostatic MIMO Radar.

[BibT_eX]

[DOI]

Renzheng Cao

Xiaofei Zhang

Wirel. Pers. Commun., 2015

Two-Dimensional Direction of Arrival Estimation Using Generalized ESPRIT Algorithm with Non-uniform L-Shaped Array.

[BibT_eX]

[DOI]

Renzheng Cao

Xiaofei Zhang

Wirel. Pers. Commun., 2015

Single Inductor Dual Buck Full-Bridge Inverter.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2015

Improving RO PUF design using frequency distribution characteristics.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

RO PUF design in FPGAs with new comparison strategies.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013

Analog Circuit Soft Fault Diagnosis based on PCA and PSO-SVM.

[BibT_eX]

[DOI]

J. Networks, 2013

2009

A Method for Logic Circuit Test Generation Based on Boolean Partial Derivative and BDD.

[BibT_eX]

[DOI]

Changqian Wang