Cheng-Ru Ho
Orcid: 0000-0002-9767-6589
According to our database1,
Cheng-Ru Ho
authored at least 13 papers
between 2015 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
7.1 A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 200Gb/s Low Power DSP-Based Optical Receiver and Transmitter with Integrated TIA and Laser Drivers.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023
2022
IEEE J. Solid State Circuits, 2022
2021
29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2018
A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter.
IEEE J. Solid State Circuits, 2017
2016
A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016
10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015