Cheng-Nan Chang
According to our database1,
Cheng-Nan Chang
authored at least 2 papers
between 2016 and 2021.
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Bibliography
2021
Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2016
J. Educ. Technol. Soc., 2016