Cheng-Kok Koh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

A Scalable Buffer Queue Sizing Algorithm for Latency Insensitive Systems.

[BibT_eX]

[DOI]

Supriyo Maji

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2019

Scalable Construction of Clock Trees With Useful Skew and High Timing Quality.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018

Clustering of flip-flops for useful-skew clock tree synthesis.

[BibT_eX]

[DOI]

Chuan Yean Tan

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Fast clock scheduling and an application to clock tree synthesis.

[BibT_eX]

[DOI]

Integr., 2017

Clock Tree Construction based on Arrival Time Constraints.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Saath: Speeding up CoFlows by Exploiting the Spatial Dimension.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on emerging Networking EXperiments and Technologies, 2017

Delay-driven layer assignment for advanced technology nodes.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

An Automatic Design of Factors in a Human-Pose Estimation System Using Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Syst. Man Cybern. Syst., 2016

Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Construction of Latency-Bounded Clock Trees.

[BibT_eX]

[DOI]

Chuan Yean Tan

Proceedings of the 2016 on International Symposium on Physical Design, 2016

MCMM clock tree optimization based on slack redistribution using a reduced slack graph.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Cost-Effective Robustness in Clock Networks Using Near-Tree Structures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Rubik: Unlocking the Power of Locality and End-point Flexibility in Cloud Scale Load Balancing.

[BibT_eX]

[DOI]

Proceedings of the 2015 USENIX Annual Technical Conference, 2015

A Useful Skew Tree Framework for Inserting Large Safety Margins.

[BibT_eX]

[DOI]

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Human-pose estimation with neural-network realization.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2015

Construction of reconfigurable clock trees for MCMM designs.

[BibT_eX]

[DOI]

Shankarshana Janarthanan

Proceedings of the 52nd Annual Design Automation Conference, 2015

Fast clock skew scheduling based on sparse-graph algorithms.

[BibT_eX]

[DOI]

Shankarshana Janarthanan

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

How to Improve Your Search Engine Ranking: Myths and Reality.

[BibT_eX]

[DOI]

Ao-Jan Su

Y. Charlie Hu

Aleksandar Kuzmanovic

ACM Trans. Web, 2014

A 3-D-Point-Cloud System for Human-Pose Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Syst. Man Cybern. Syst., 2014

Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design.

[BibT_eX]

[DOI]

Chin Ngai Sze

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

MIP-based detailed placer for mixed-size circuits.

[BibT_eX]

[DOI]

Shuai Li

Proceedings of the International Symposium on Physical Design, 2014

Selecting best viewpoint for human-pose estimation.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Robotics and Automation, 2014

A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A study on the use of parallel wiring techniques for sub-20nm designs.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Analytical placement of mixed-size circuits for better detailed-routability.

[BibT_eX]

[DOI]

Shuai Li

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Guest editorial: Special section on cross-domain physical optimization.

[BibT_eX]

[DOI]

Jiang Hu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Analytical estimates of stress around a doubly periodic arrangement of through-silicon vias.

[BibT_eX]

[DOI]

Anirudh Udupa

Ganesh Subbarayan

Microelectron. Reliab., 2013

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2013

Collaborative object tracking with motion similarity measure.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2013

Case study for placement solutions in ispd11 and dac12 routability-driven placement contests.

[BibT_eX]

[DOI]

Wen-Hao Liu

Yih-Lang Li

Proceedings of the International Symposium on Physical Design, 2013

Local merges for effective redundancy in clock networks.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

Using action classification for human-pose estimation.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2013

A 3D-point-cloud feature for human-pose estimation.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Conference on Robotics and Automation, 2013

Optimization of placement solutions for routability.

[BibT_eX]

[DOI]

Wen-Hao Liu

Yih-Lang Li

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits.

[BibT_eX]

[DOI]

Jongwon Lee

Duo Chen

Dan Jiao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Guest Editorial Special Section on the 2011 International Symposium on Physical Design.

[BibT_eX]

[DOI]

Jiang Hu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A two-dimensional domain decomposition technique for the simulation of quantum-scale devices.

[BibT_eX]

[DOI]

Gerhard Klimeck

J. Comput. Phys., 2012

A size scaling approach for mixed-size placement.

[BibT_eX]

[DOI]

Kalliopi Tsota

Proceedings of the International Symposium on Physical Design, 2012

Mixed integer programming models for detailed placement.

[BibT_eX]

[DOI]

Shuai Li

Proceedings of the International Symposium on Physical Design, 2012

A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing.

[BibT_eX]

[DOI]

Wen-Hao Liu

Yih-Lang Li

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

A parallel branch-and-cut approach for detailed placement.

[BibT_eX]

[DOI]

Y. Charlie Hu

ACM Trans. Design Autom. Electr. Syst., 2011

Finite difference schemes for heat conduction analysis in integrated circuit design and manufacturing.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2011

Cross link insertion for improving tolerance to variations in clock network synthesis.

[BibT_eX]

[DOI]

Tarun Mittal

Proceedings of the 2011 International Symposium on Physical Design, 2011

Synthesis of low power clock trees for handling power-supply variations.

[BibT_eX]

[DOI]

Shashank Bujimalla

Proceedings of the 2011 International Symposium on Physical Design, 2011

Processor caches with multi-level spin-transfer torque ram cells.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Simultaneous redundant via insertion and line end extension for yield optimization.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Optimal Double Via Insertion With On-Track Preference.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

How to Improve Your Google Ranking: Myths and Reality.

[BibT_eX]

[DOI]

Ao-Jan Su

Y. Charlie Hu

Aleksandar Kuzmanovic

Proceedings of the 2010 IEEE/WIC/ACM International Conference on Web Intelligence, 2010

PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009

Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Tolerating process variations in large, set-associative caches: The buddy cache.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2009

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

A study of routability estimation and clustering in placement.

[BibT_eX]

[DOI]

Kalliopi Tsota

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction.

[BibT_eX]

[DOI]

Wenwen Chai

Dan Jiao

Proceedings of the 46th Design Automation Conference, 2009

2008

Global Interconnect Planning.

[BibT_eX]

[DOI]

Evangeline F. Y. Young

Yao-Wen Chang

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Fast and Optimal Redundant Via Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Optimal post-routing redundant via insertion.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

A fast band matching technique for impedance extraction.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Guiding global placement with wire density.

[BibT_eX]

[DOI]

Kalliopi Tsota

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Corrections to "Exact and Numerically Stable Closed-Form Expressions for Potential Coefficients of Rectangular Conductors".

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Routability-Driven Placement and White Space Allocation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Statistical Timing Analysis Considering Spatial Correlations.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement.

[BibT_eX]

[DOI]

Chen Li

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

VOSCH: Voltage scaled cache hierarchies.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

A frequency-domain technique for statistical timing analysis of clock meshes.

[BibT_eX]

[DOI]

Ruilin Wang

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A fast band-matching technique for interconnect inductance modeling.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006

Postlayout optimization for synthesis of Domino circuits.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

Exact and numerically stable closed-form expressions for potential coefficients of rectangular conductors.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction.

[BibT_eX]

[DOI]

Ngai Wong

Tung-Sang Ng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Performance analysis of latency-insensitive systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Stable and compact inductance modeling of 3-D interconnect structures.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Clock Generation and Distribution Using Traveling-Wave Oscillators with Reflection and Regeneration.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Adaptive admittance-based conductor meshing for interconnect analysis.

[BibT_eX]

[DOI]

Ya-Chi Yang

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Synthesis of skewed logic circuits.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

Mixed block placement via fractional cut recursive bisection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Cascaded carry-select adder (C<sup>2</sup>SA): a new structure for low-power CSA design.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Statistical based link insertion for robust clock network design.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

3D module placement for congestion and power noise reduction.

[BibT_eX]

[DOI]

Jacob R. Minz

Sung Kyu Lim

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Improving the scalability of SAMBA bus architecture.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Floorplan management: incremental placement for gate sizing and buffer insertion.

[BibT_eX]

[DOI]

Chen Li

Patrick H. Madden

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Compact and stable modeling of partial inductance and reluctance matrices.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Process variation robust clock tree routing.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Post-layout logic duplication for synthesis of domino circuits with complex gates.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A Performance and Power Co-optimization Approach for Modern Processors.

[BibT_eX]

[DOI]

Yongxin Zhu

Weng-Fai Wong

Proceedings of the Fifth International Conference on Computer and Information Technology (CIT 2005), 2005

2004

Recursive bisection based mixed block placement.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Physical Design, 2004

Fast simulation of VLSI interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A fast Newton/Smith algorithm for solving algebraic Riccati equations and its application in model order reduction.

[BibT_eX]

[DOI]

Ngai Wong

Tung-Sang Ng

Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Passivity-preserving model reduction via a computationally efficient project-and-balance scheme.

[BibT_eX]

[DOI]

Ngai Wong

Proceedings of the 41th Design Automation Conference, 2004

Post-layout logic optimization of domino circuits.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

A high performance bus communication architecture through bus splitting.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

On-chip interconnect modeling by wire duplication.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy.

[BibT_eX]

[DOI]

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Non-Crossing OBDDs for Mapping to Regular Circuit Structures.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Interconnect Planning with Local Area Constrained Retiming.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

An adaptive window-based susceptance extraction and its efficient implementation.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

A metric for analyzing effective on-chip inductive coupling.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Integer linear programming-based synthesis of skewed logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

UST/DME: a clock tree router for general skew constraints.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2002

Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods.

[BibT_eX]

[DOI]

Q. Su

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Power Supply Noise Suppression via Clock Skew Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Synthesis of Selectively Clocked Skewed Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Flip-Flop and Repeater Insertion for Early Interconnect Planning.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

A factorization-based framework for passivity-preserving model reduction of RLC systems.

[BibT_eX]

[DOI]

Q. Su

Proceedings of the 39th Design Automation Conference, 2002

2001

Routability-driven repeater block planning for interconnect-centricfloorplanning.

[BibT_eX]

[DOI]

Probir Sarkar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Interconnect layout optimization under higher order RLC model forMCM designs.

[BibT_eX]

[DOI]

Patrick H. Madden

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Interconnect sizing and spacing with consideration of couplingcapacitance.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Decoupling capacitance allocation for power supply noise suppression.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Physical Design, 2001

Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Power trends and performance characterization of 3-dimensional integration.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Short-circuit power analysis of an inverter driving an RLC load.

[BibT_eX]

[DOI]

Rui Wang

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Repeater block planning under simultaneous delay and transition time constraints.

[BibT_eX]

[DOI]

Probir Sarkar

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

Efficient balance-and-truncate model reduction for large scale systems.

[BibT_eX]

[DOI]

V. Balakrishnan

Q. Su

Proceedings of the American Control Conference, 2001

2000

Routability-driven repeater block planning for interconnect-centric floorplanning.

[BibT_eX]

[DOI]

Probir Sarkar

Vivek Sundararaman

Proceedings of the 2000 International Symposium on Physical Design, 2000

Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family.

[BibT_eX]

[DOI]

Alexandre Solomatnikov

Dinesh Somasekhar

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Frequency Domain Analysis of Switching Noise on Power Supply Network.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures.

[BibT_eX]

[DOI]

Patrick H. Madden

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Power minimization by simultaneous dual-V<sub>th</sub> assignment and gate-sizing.

[BibT_eX]

[DOI]

Liqiong Wei

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1998

Bounded-skew clock and Steiner routing.

[BibT_eX]

[DOI]

Andrew B. Kahng

ACM Trans. Design Autom. Electr. Syst., 1998

1997

Interconnect design for deep submicron ICs.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Interconnect layout optimization under higher-order RLC model.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Global interconnect sizing and spacing with consideration of coupling capacitance.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

Performance optimization of VLSI interconnect layout.

[BibT_eX]

[DOI]

Integr., 1996

Simultaneous buffer and wire sizing for performance and power optimization.

[BibT_eX]

[DOI]

Kwok-Shing Leung

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995

Minimum-Cost Bounded-Skew Clock Routing.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Bounded-skew clock and Steiner routing under Elmore delay.

[BibT_eX]

[DOI]

Andrew B. Kahng

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

Simultaneous driver and wire sizing for performance and power optimization.

[BibT_eX]

[DOI]