Cheng-Hsueh Tsai

According to our database, Cheng-Hsueh Tsai authored at least 8 papers between 2014 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Design and Analysis of 55-63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS.

Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx

IEEE J. Solid State Circuits, 2022

2021

A 55-63 GHz fundamental Quad-Core VCO with NMOS-only stacked oscillator in 28 nm CMOS.

Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx

Proceedings of the 47th ESSCIRC 2021, 2021

2020

Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication.

Cheng-Hsueh Tsai, Zhiwei Zong, Federico Pepe, Giovanni Mangraviti, Jan Craninckx, Piet Wambacq

IEEE J. Solid State Circuits, 2020

2019

A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter.

Cheng-Hsueh Tsai, Federico Pepe, Giovanni Mangraviti, Zhiwei Zong, Jan Craninckx, Piet Wambacq

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper).

Aritra Banerjee, Kristof Vaesen, Akshay Visweswaran, Khaled Khalaf, Qixian Shi, Steven Brebels, Davide Guermandi, Cheng-Hsueh Tsai, Johan Nguyen, Alaa Medra, Yao Liu, Giovanni Mangraviti, Orges Furxhi, Bert Gyselinckx, André Bourdoux, Jan Craninckx, Piet Wambacq

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2017

A 54-64.8 GHz subharmonically injection-locked frequency synthesizer with transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS.

Cheng-Hsueh Tsai, Giovanni Mangraviti, Qixian Shi, Khaled Khalaf, André Bourdoux, Piet Wambacq

Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016

An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique.

Tsung-Han Tsai, Hung-Yen Tai, Pao-Yang Tsai, Cheng-Hsueh Tsai, Hsin-Shu Chen

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2014

A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS.

Hung-Yen Tai, Cheng-Hsueh Tsai, Pao-Yang Tsai, Hung-Wei Chen, Hsin-Shu Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2014