Cheng-An Chien

According to our database¹, Cheng-An Chien authored at least 18 papers between 2008 and 2014.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2014

A 360-degree panoramic video system design.

[BibT_eX]

[DOI]

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

2013

Real-Time 3D Depth Generation for Stereoscopic Video Applications with Thread-Level Superscalar-Pipeline Parallelization.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2013

A view scalable multi-view video decoder system.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

High efficiency data access system architecture for deblocking filter supporting multiple video coding standards.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2012

A Verification-Aware Design Methodology for Thread Pipelining Parallelization.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2012

3D depth map generation for embedded stereo applications.

[BibT_eX]

[DOI]

Proceedings of the 2012 Visual Communications and Image Processing, 2012

A two level mode decision algorithm for H.264 high profile intra encoding.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An inter-frame/inter-view cache architecture design for multi-view video decoders.

[BibT_eX]

[DOI]

Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012

2011

A low-power management technique for high-performance domino circuits.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2009

A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards.

[BibT_eX]

[DOI]

Cheng-An Chien

Hsiu-Cheng Chang

Jiun-In Guo

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Multi-standard Video Decoder for High Definition Video Applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Dynamic Quality-scalable H.264 Video Encoder.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A dynamic quality-scalable H.264 video encoder chip.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A high throughput in-loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding.

[BibT_eX]

[DOI]

Cheng-An Chien

Hsiu-Cheng Chang

Jiun-In Guo

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Cheng-An Chien

Timeline

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On csauthors.net:

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