Chen-Yong Cher
According to our database1,
Chen-Yong Cher
authored at least 42 papers
between 2001 and 2018.
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Bibliography
2018
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2016
Proceedings of the International Conference for High Performance Computing, 2016
Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
IBM J. Res. Dev., 2015
Proceedings of the International Conference for High Performance Computing, 2015
Experience report: An application-specific checkpointing technique for minimizing checkpoint corruption.
Proceedings of the 26th IEEE International Symposium on Software Reliability Engineering, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the International Conference for High Performance Computing, 2014
Understanding Soft Error Resiliency of Blue Gene/Q Compute Chip through Hardware Proton Irradiation and Software Fault Injection.
Proceedings of the International Conference for High Performance Computing, 2014
Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation.
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Exploring the effects of on-chip thermal variation on high-performance multicore architectures.
ACM Trans. Archit. Code Optim., 2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
A wire-speed power<sup>TM</sup> processor: 2.3GHz 45nm SOI with 16 cores and 64 threads.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 7th Conference on Computing Frontiers, 2010
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
2009
Temperature Variation Characterization and Thermal Management of Multicore Architectures.
IEEE Micro, 2009
2008
Proceedings of the 4th International Conference on Virtual Execution Environments, 2008
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
Proceedings of the 26th International Conference on Computer Design, 2008
2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
2006
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006
Proceedings of the Architecture of Computing Systems, 2006
2005
Combined circuit and architectural level variable supply-voltage scaling for low power.
IEEE Trans. Very Large Scale Integr. Syst., 2005
2004
Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign.
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004
2003
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003
2001
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001