Chen Wang
Orcid: 0000-0001-8928-5863Affiliations:
- Mentor Graphics Corporation, Wilsonville, OR, USA
- University of Iowa, Iowa City, IA, USA (PhD 2003)
According to our database1,
Chen Wang
authored at least 22 papers
between 2001 and 2022.
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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Bibliography
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.
Proceedings of the IEEE International Test Conference, 2020
2019
Proceedings of the 28th IEEE Asian Test Symposium, 2019
2018
Proceedings of the IEEE International Test Conference, 2018
2017
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
2014
Proceedings of the 2014 International Test Conference, 2014
2013
Proceedings of the 2013 IEEE International Test Conference, 2013
2007
J. Electron. Test., 2007
2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 10th European Test Symposium, 2005
2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
2001
REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001