Chen Li

Orcid: 0000-0002-0684-1754

Affiliations:
  • National University of Defense Technology, Changsha, China


According to our database1, Chen Li authored at least 19 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2024
LWECC: A Lightweight ECC Technology for HPC Accelerators Supporting Multi-granularity Memory Access.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2022
Adaptive Low-Cost Loop Expansion for Modulo Scheduling.
Proceedings of the Network and Parallel Computing, 2022

2021
Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions.
CCF Trans. High Perform. Comput., 2021

Improving Inter-kernel Data Reuse With CTA-Page Coordination in GPGPU.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020
A Dynamic and Proactive GPU Preemption Mechanism Using Checkpointing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Active one-shot learning by a deep Q-network strategy.
Neurocomputing, 2020

2019
Priority-Based PCIe Scheduling for Multi-Tenant Multi-GPU Systems.
IEEE Comput. Archit. Lett., 2019

A Reinforcement One-Shot Active Learning Approach for Aircraft Type Recognition.
IEEE Access, 2019

Load-Balanced Link Distribution in Mesh-Based Many-Core Systems.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

A Framework for Memory Oversubscription Management in Graphics Processing Units.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
PEP: proactive checkpointing for efficient preemption on GPUs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
A high performance reliable NoC router.
Integr., 2017

Fairness-oriented switch allocation for networks-on-chip.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Fairness-Oriented and Location-Aware NUCA for Many-Core SoC.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

2016
A heterogeneous low-cost and low-latency Ring-Chain network for GPGPUs.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Overcoming and Analyzing the Bottleneck of Interposer Network in 2.5D NoC Architecture.
Proceedings of the Advanced Computer Architecture - 11th Conference, 2016

2015
Express Ring: a multi-layer and non-blocking NoC architecture.
IEICE Electron. Express, 2015

Adaptive remaining hop count flow control: Consider the interaction between packets.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015


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