Chen Kong Teh

According to our database, Chen Kong Teh authored at least 8 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

730-790mA/mm² 48V-to-1V Integrated Hybrid DC-DC Converters Based on a Star-Delta Switching Network with 5x/8x Duty Expansion.

Chen Kong Teh, Te Bi, Shuichi Ito, Takashi Kurihara

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2018

An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer.

Shusuke Kawai, Hiromitsu Aoyama, Rui Ito, Yutaka Shimizu, Mitsuyuki Ashida, Asuka Maki, Tomohiko Takeuchi, Hiroyuki Kobayashi, Go Urakawa, Hiroaki Hoshino, Shigehito Saigusa, Kazushi Koyama, Makoto Morita, Ryuichi Nihei, Daisuke Goto, Motoki Nagata, Kengo Nakata, Katsuyuki Ikeuchi, Kentaro Yoshioka, Ryoichi Tachibana, Makoto Arai, Chen Kong Teh, Atsushi Suzuki, Hiroshi Yoshida, Yosuke Hagiwara, Takayuki Kato, Ichiro Seto, Tomoya Horiguchi, Koichiro Ban, Kyosuke Takahashi, Hirotsugu Kajihara, Toshiyuki Yamagishi, Yuki Fujimura, Kazuhisa Horiuchi, Katsuya Nonin, Kengo Kurose, Hideki Yamada, Kentaro Taniguchi, Masahiro Sekiya, Takeshi Tomizawa, Daisuke Taki, Masaaki Ikuta, Tomoya Suzuki, Yuki Ando, Daisuke Yashima, Takahisa Kaihotsu, Hiroki Mori, Kensuke Nakanishi, Takeshi Kumagaya, Yasuo Unekawa, Tsuguhide Aoki, Kohei Onizuka, Toshiya Mitomo

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2016

12.3 A 2-output step-up/step-down switched-capacitor DC-DC converter with 95.8% peak efficiency and 0.85-to-3.6V input voltage range.

Chen Kong Teh, Atsushi Suzuki

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014

4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control.

Chen Kong Teh, Atsushi Suzuki, Manabu Yamada, Mototsugu Hamada, Yasuo Unekawa

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2011

A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS.

Chen Kong Teh, Tetsuya Fujita, Hiroyuki Hara, Mototsugu Hamada

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2008

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.

Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems.

Chen Kong Teh, Mototsugu Hamada, Tetsuya Fujita, Hiroyuki Hara, N. Ikumi, Yukihito Oowaki

IEEE Trans. Very Large Scale Integr. Syst., 2006

2005

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI.

Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005