Chen-Huan Chiang

According to our database, Chen-Huan Chiang authored at least 15 papers between 1994 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

Design for Bit Error Rate estimation of high speed serial links.

Ujjwal Guin, Chen-Huan Chiang

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2010

A Common Language Framework for Next-Generation Embedded Testing.

Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook

IEEE Des. Test Comput., 2010

2008

Problems Using Boundary-Scan for Memory Cluster Tests.

Bradford G. Van Treuren, Chen-Huan Chiang, Kenneth Honaker

Proceedings of the 2008 IEEE International Test Conference, 2008

A New Language Approach for IJTAG.

Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

FPGA Prototyping of a Scan Based System-On-Chip Design.

Brendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook

Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

A practical approach to comprehensive system test & debug using boundary scan based test architecture.

Tapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren

Proceedings of the 2007 IEEE International Test Conference, 2007

2004

Testing and Remote Field Update of Distributed Base Stations in a Wireless Network.

Chen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2002

A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur.

Tapan J. Chakraborty, Chen-Huan Chiang

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2000

BIST TPG for Combinational Cluster Interconnect Testing at Board Level.

Chen-Huan Chiang, Sandeep K. Gupta

J. Electron. Test., 2000

End-to-end testing for boards and systems using boundary scan.

Robert W. Barr, Chen-Huan Chiang, Edward L. Wallace

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

BIST TPG for SRAM cluster interconnect testing at board level.

Chen-Huan Chiang, Sandeep K. Gupta

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1998

BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level.

Chen-Huan Chiang, Sandeep K. Gupta

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

BIST TPGs for Faults in Board Level Interconnect via Boundary Scan.

Chen-Huan Chiang, Sandeep K. Gupta

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

BIST TPG for faults in system backplanes.

Chen-Huan Chiang, Sandeep K. Gupta

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1994

Random pattern testable logic synthesis.

Chen-Huan Chiang, Sandeep K. Gupta

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994