Chen-Chien Lin

According to our database, Chen-Chien Lin authored at least 4 papers between 2011 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta-Sigma Modulator.

Chen-Chien Lin, Chan-Hsiang Weng, Tzu-An Wei, Yung-Yu Lin, Tsung-Hsien Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2014

2013

A low-power dual-mode continuous-time delta-sigma modulator with a folded quantizer.

Chen-Chien Lin, Chan-Hsiang Weng, Tsung-Hsien Lin

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2011

A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation.

Chan-Hsiang Weng, Chen-Chien Lin, Yu-Cheng Chang, Tsung-Hsien Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 4MHz BW 69dB SNDR continuous-time delta-sigma modulator with reduced sensitivity to clock jitter.

Yu-Cheng Chang, Wei-Hao Chiu, Chen-Chien Lin, Tsung-Hsien Lin

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011