Chen Chen

According to our database, Chen Chen authored at least 16 papers between 2015 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography.

Yifan Zhao, Honglin Kuang, Yi Sun, Zhen Yang, Chen Chen, Jianyi Meng, Jun Han

Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

2020

Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product.

Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Xuantie-910: Innovating Cloud and Edge Computing by RISC-V.

Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi

Proceedings of the IEEE Hot Chips 32 Symposium, 2020

2018

An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs.

Yan He, Jianyi Meng, Zhijian Chen, Xiaoyan Xiang, Chen Chen

IEICE Electron. Express, 2018

2017

An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror.

Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng

IEEE Trans. Very Large Scale Integr. Syst., 2017

A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction.

Sheng Wang, Chen Chen, Xiaoyan Xiang, Jian-Yi Meng

IEEE Trans. Very Large Scale Integr. Syst., 2017

SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor.

Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng

IEICE Electron. Express, 2017

A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs.

Sheng Wang, Chen Chen, Xiaoyan Xiang, Jianyi Meng

IEICE Electron. Express, 2017

A new error masking flip-flop with one cycle correction penalty.

Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A light-weight energy-efficient resilient circuit for variation tolerance.

Xiaopei Chen, Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor.

Zhenqiang Yong, Xiaoyan Xiang, Jianyi Meng, Chen Chen

IEICE Electron. Express, 2016

EDSU: Error detection and sampling unified flip-flop with ultra-low overhead.

Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng, Yong Ding, Xiaolang Yan

IEICE Electron. Express, 2016

Value locality based storage compression memory architecture for ECG sensor node.

Chaojun Zhao, Chen Chen, Zhijian Chen, Jianyi Meng

Sci. China Inf. Sci., 2016

2015

A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction.

Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

An energy-efficient microprocessor using multilevel error correction for timing error tolerance.

Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A timing failure tolerance design with in-field simultaneous error detection and correction.

Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015