Chee-Kian Ong

According to our database, Chee-Kian Ong authored at least 12 papers between 2000 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

A Clock-Less Jitter Spectral Analysis Technique.

Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2006

Bit-Error-Rate Estimation for High-Speed Serial Links.

Dongwoo Hong, Chee-Kian Ong, Kwang-Ting (Tim) Cheng

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

2004

A new sigma-delta modulator architecture for testing using digital stimulus.

Chee-Kian Ong, Kwang-Ting Cheng, Li-C. Wang

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A Scalable On-Chip Jitter Extraction Technique.

Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics.

Dongwoo Hong, Chee-Kian Ong, Kwang-Ting (Tim) Cheng

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Random Jitter Extraction Technique in a Multi-Gigahertz Signal.

Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang

Proceedings of the 2004 Design, 2004

Jitter spectral extraction for multi-gigahertz signal.

Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Delta-sigma modulator based mixed-signal BIST architecture for SoC.

Chee-Kian Ong, Kwang-Ting (Tim) Cheng, Li-C. Wang

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus.

Chee-Kian Ong, Kwang-Ting (Tim) Cheng

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

2000

Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test.

Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

A BIST Scheme for On-Chip ADC and DAC Testing.

Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng

Proceedings of the 2000 Design, 2000

An FPGA-based re-configurable functional tester for memory chips.

Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000