Chauchin Su

According to our database, Chauchin Su authored at least 76 papers between 1990 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation.

Ting-You Lin, Chauchin Su, Chung-Chih Hung, Karuna Nidhi, Chily Tu, Shao-Chang Huang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2017

LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs.

Ting-You Lin, Yingchieh Ho, Chauchin Su

Sensors, 2017

2016

A 0.5V/22 μW low power transceiver IC for use in ESC intra-body communication system.

Yuhwai Tseng, Ting-You Lin, Songwen Yau, Yingchieh Ho, Chauchin Su

Proceedings of the International SoC Design Conference, 2016

2014

A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications.

Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Chauchin Su, Chen-Yi Lee

IEEE J. Solid State Circuits, 2014

A low-power analog-to-digital converter with digitalized amplifier for PAM systems.

Yingchieh Ho, Chou-Ming Kuo, Chauchin Su

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013

A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO.

Yingchieh Ho, Yu-Sheng Yang, Chiachi Chang, Chauchin Su

IEEE J. Solid State Circuits, 2013

2012

Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique.

Yingchieh Ho, Chiachi Chang, Chauchin Su

IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 0.09 µW Low Power Front-End Biopotential Amplifier for Biosignal Recording.

Yuhwai Tseng, Yingchieh Ho, Shuoting Kao, Chauchin Su

IEEE Trans. Biomed. Circuits Syst., 2012

A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters.

Yingchieh Ho, Chauchin Su

IEEE J. Solid State Circuits, 2012

Cumulative Differential Nonlinearity Testing of ADCs.

Hung-Kai Chen, Yingchieh Ho, Chauchin Su

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers.

Yingchieh Ho, Hung-Kai Chen, Chauchin Su

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications.

Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Siou-Ming Chuang, Tze-Zheng Yang, Po-Chun Liu, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee

Proceedings of the Symposium on VLSI Circuits, 2012

2011

A 0.2-0.6 V ring oscillator design using bootstrap technique.

Yingchieh Ho, Yu-Sheng Yang, Chauchin Su

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

Timing Jitter and Modulation Profile Extraction for Spread-Spectrum Clocks.

Jen-Chien Hsu, Chauchin Su

IEEE Trans. Instrum. Meas., 2010

Measurement and Evaluation of the Bioelectrical Impedance of the Human Body by Deconvolution of a Square Wave.

Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu

IEICE Trans. Inf. Syst., 2010

Measuring the Transmission Characteristic of the Human Body in an Electrostatic-Coupling Intra Body Communication System Using a Square Test Stimulus.

Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A 5Gb/s pulse signaling interface for low power on-chip data communication.

Hung-Wen Lin, Yingchieh Ho, YingLin Fa, Chauchin Su

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus.

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen

IEEE Trans. Very Large Scale Integr. Syst., 2009

Design of an All-Digital LVDS Driver.

Hungwen Lu, Hsin-Wen Wang, Chauchin Su, Chien-Nan Jimmy Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A Tree-Topology Multiplexer for Multiphase Clock System.

Hungwen Lu, Chauchin Su, Chien-Nan Jimmy Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System.

Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu

IEICE Trans. Commun., 2009

2008

BIST for Measuring Clock Jitter of Charge-Pump Phase-Locked Loops.

Jen-Chien Hsu, Chauchin Su

IEEE Trans. Instrum. Meas., 2008

Long-Range Prediction for Real-Time MPEG Video Traffic: An H_infty Filter Approach.

Chih-Hu Wang, Bor-Sen Chen, Bore-Kuen Lee, Tsu-Tian Lee, Chien-Nan Jimmy Liu, Chauchin Su

IEEE Trans. Circuits Syst. Video Technol., 2008

A Scalable Digitalized Buffer for Gigabit I/O.

Hungwen Lu, Chauchin Su, Chien-Nan Jimmy Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2008

2007

Multilevel Full-Chip Routing With Testability and Yield Enhancement.

Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection.

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen

J. Electron. Test., 2007

A Test and Diagnosis Methodology for RF Transceivers.

Hung-Kai Chen, Chauchin Su

Proceedings of the 16th Asian Test Symposium, 2007

2006

IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults.

Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems.

Wenliang Tseng, Chien-Nan Jimmy Liu, Chauchin Su

IEICE Trans. Electron., 2006

Estimation of Loss Coefficients of Nonlinear Rubber Using Iterative H∞ Filter.

Chih-Hu Wang, Bore-Kuen Lee, Wei-Hang Tseng, Chung-Hsi Fu, Chauchin Su, Chien-Nan Jimmy Liu

Proceedings of the IEEE International Conference on Systems, 2006

A Digital BIST Methodology for Spread Spectrum Clock Generators.

Maohsuan Chou, Jen-Chien Hsu, Chauchin Su

Proceedings of the 15th Asian Test Symposium, 2006

2005

A spread spectrum clock generator for SATA-II.

Wei-Ta Chen, Jen-Chien Hsu, Hong-Wen Lune, Chauchin Su

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Finite State Machine Synthesis for At-Speed Oscillation Testability.

Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Oscillation ring based interconnect test scheme for SOC.

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI.

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

1149.4 Based On-Line Quiescent State Monitoring Technique.

Chauchin Su, Chih-Hu Wang, Wei-Juo Wang, I. S. Tseng

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A novel LCD driver testing technique using logic test channels.

Chauchin Su, Wei-Juo Wang, Chih-Hu Wang, I. S. Tseng

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing.

Chih-Wen Lu, Chung-Len Lee, Chauchin Su, Jwu-E Chen

J. Electron. Test., 2002

Guest Editorial.

Kuen-Jong Lee, Chau-Chin Su

J. Electron. Test., 2002

A Self Calibrated ADC BIST Methodology.

Hung-Kai Chen, Chih-Hu Wang, Chau-Chin Su

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

2001

Intrinsic response for analog module testing using an analog testability bus.

Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou

ACM Trans. Design Autom. Electr. Syst., 2001

Fault Diagnosis for Linear Analog Circuits.

Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen

J. Electron. Test., 2001

Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization.

Yue-Tsang Chen, Chauchin Su

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Configuration free SoC interconnect BIST methodology.

Chauchin Su, Wenliang Tseng

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A computer aided engineering system for memory BIST.

Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee

Proceedings of ASP-DAC 2001, 2001

2000

Intrinsic response extraction for the removal of the parasiticeffects in analog test buses.

Chauchin Su, Yue-Tsang Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis.

Chauchin Su, Yue-Tsang Chen, Shenshung Chiang

J. Inf. Sci. Eng., 2000

A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier.

Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su

J. Inf. Sci. Eng., 2000

Crosstalk Effect Removal for Analog Measurement in Analog Test Bus.

Chauchin Su, Yue-Tsang Chen

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses.

Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee

Proceedings of the 2000 Design, 2000

Is IDDQ testing not applicable for deep submicron VLSI in year 2011?

Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A methodology for fault model development for hierarchical linear systems.

Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Decentralized BIST Methodology for System Level Interconnects.

Chauchin Su, Shyh-Jye Jou

J. Electron. Test., 1999

Analog Metrology and Stimulus Selection in a Noisy Environment.

Chauchin Su, Yue-Tsang Chen, Chung-Len Lee

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Boundary scan BIST methodology for reconfigurable systems.

Chauchin Su, Shung-Won Jeng, Yue-Tsang Chen

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

A linear optimal test generation algorithm for interconnect testing.

Chauchin Su

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Comprehensive Interconnect BIST Methodology for Virtual Socket Interface.

Chauchin Su, Yue-Tsung Chen

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Analog Module Metrology Using MNABST-1 P1149.4 Test Chip.

Yue-Tsang Chen, Chauchin Su

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design.

Shyh-Jye Jou, Chang-Yu Chen, En-Chung Yang, Chau-Chin Su

IEEE J. Solid State Circuits, 1997

Parasitic Effect Removal for Analog Measurement in P1149.4 Environment.

Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Analog signal metrology for mixed signal ICs.

Chauchin Su, Yi-Ren Cheng, Yue-Tsang Chen, Shing Tenchen

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

Structural approach for performance driven ECC circuit synthesis.

Chauchin Su, Kathy Y. Chen, Shyh-Jye Jou

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Metrology for analog module testing using analog testability bus.

Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Decentralized BIST for 1149.1 and 1149.5 Based Interconnects.

Chauchin Su, Shyh-Jye Jou, Yuan-Tzu Ting

Proceedings of the 1996 European Design and Test Conference, 1996

Syndrome Simulation And Syndrome Test For Unscanned Interconnects.

Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Circuits Design Optimization Using Symbolic Approach.

Shyh-Jye Jou, Kou-Fong Liu, Chauchin Su

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors.

Wen-Hsing Hsieh, Shyh-Jye Jou, Chauchin Su

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Impulse response fault model and fault extraction for functional level analog circuit diagnosis.

Chauchin Su, Shenshung Chiang, Shyh-Jye Jou

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

An I_DDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment.

Chauchin Su, Kychin Hwang, Shyh-Jye Jou

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits.

Shyh-Jye Jou, Mei-Fang Perng, Chauchin Su, C. K. Wang

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Random Testing of Interconnects in A Boundary Scan Environment.

Chauchin Su

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

A Serial-Scan Test-Vector-Compression Methodology.

Chauchin Su, Kychin Hwang

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

ECCSyn: a Synthesis Tool for ECC Circuits.

Chauchin Su, Jyrghong Wang

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A Universal BIST Methodology for Interconnects.

Chiyuan Chang, Chauchin Su

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1990

Computer-aided design of pseudoexhaustive BIST for semiregular circuits.

Chau-Chin Su, Charles R. Kime

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Multiple path sensitization for hierarchical circuit testing.

Chau-Chin Su, Charles R. Kime

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990