Chau-Shen Chen

According to our database, Chau-Shen Chen authored at least 6 papers between 1993 and 2001.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2001

Architecture driven circuit partitioning.

Chau-Shen Chen, TingTing Hwang, C. L. Liu

IEEE Trans. Very Large Scale Integr. Syst., 2001

1998

Layout Driven Selection and Chaining of Partial Scan Flip-Flops.

Chau-Shen Chen, TingTing Hwang

J. Electron. Test., 1998

1997

Low Power FPGA Design - A Re-engineering Approach.

Chau-Shen Chen, TingTing Hwang, C. L. Liu

Proceedings of the 34st Conference on Design Automation, 1997

1996

Layout Driven Selecting and Chaining of Partial Scan.

Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang

Proceedings of the 33st Conference on Design Automation, 1996

1995

Combining technology mapping and placement for delay-minimization in FPGA designs.

Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1993

Combining technology mapping and placement for delay-optimization in FPGA designs.

Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993