Charlie Hwang

According to our database, Charlie Hwang authored at least 4 papers between 2007 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.

John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Cao

IEEE J. Solid State Circuits, 2011

A 90 nm 16 Mb embedded phase-change memory macro with write current smoothing and enhanced write bandwidth.

Hongwei Hong, Zheng Li, Qin Li, Ruizhe Wang, Charlie Hwang

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache.

John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, Nianzheng Cao

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2007

Power-constrained high-frequency circuits for the IBM POWER6 microprocessor.

Brian W. Curran, Eric Fluhr, Jose Paredes, Leon J. Sigal, Joshua Friedrich, Yiu-Hing Chan, Charlie Hwang

IBM J. Res. Dev., 2007