Charles C. Weems

Orcid: 0000-0002-8535-0258

Affiliations:
  • University of Massachusetts Amherst, USA


According to our database1, Charles C. Weems authored at least 90 papers between 1983 and 2023.

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Bibliography

2023
NSF/IEEE-TCPP Curriculum on Parallel and Distributed Computing for Undergraduates - Version II - Big Data, Energy, and Distributed Computing.
Proceedings of the 54th ACM Technical Symposium on Computer Science Education, Volume 2, 2023

Integrating Parallel and Distributed Computing in Early Computing Classes.
Proceedings of the 54th ACM Technical Symposium on Computer Science Education, Volume 2, 2023

2022
Integrating Parallel and Distributed Computing in Early CS Courses.
Proceedings of the SIGCSE 2022: The 53rd ACM Technical Symposium on Computer Science Education, 2022

2021
DPF-ECC: A Framework for Efficient ECC With Double Precision Floating-Point Computing Power.
IEEE Trans. Inf. Forensics Secur., 2021

EduHiPC 2021 Keynote Talk: Early Parallel and Distributed Computing Education: Canary in the Coal Mine.
Proceedings of the 28th IEEE International Conference on High Performance Computing, 2021

2020
DPF-ECC: Accelerating Elliptic Curve Cryptography with Floating-Point Computing Power of GPUs.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020

2019
Modernizing Early CS Courses with Parallel and Distributed Computing.
Proceedings of the 50th ACM Technical Symposium on Computer Science Education, 2019

2018
The smallest eigenvalue of large Hankel matrices.
Appl. Math. Comput., 2018

NSF/IEEE-TCPP Curriculum Initiative on Parallel and Distributed Computing: Status Report.
Proceedings of the 49th ACM Technical Symposium on Computer Science Education, 2018

sDPF-RSA: Utilizing Floating-point Computing Power of GPUs for Massive Digital Signature Computations.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

A New Variant of the Barrett Algorithm Applied to Quotient Selection.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

Faster Modular Exponentiation Using Double Precision Floating Point Arithmetic on the GPU.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

Editors' Introduction and Roadmap.
Proceedings of the Topics in Parallel and Distributed Computing, 2018

2016
Asymptotic Optimality of Parallel Short Division.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

Optimizing Modular Multiplication for NVIDIA's Maxwell GPUs.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2015
A New Memory-Disk Integrated System with HW Optimizer.
ACM Trans. Archit. Code Optim., 2015

HIPS-LSPP Introduction and Committees.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Pushing the Performance Envelope of Modular Exponentiation Across Multiple Generations of GPUs.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015

2014
VLSI Design of a Large-Number Multiplier for Fully Homomorphic Encryption.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Guest Editors' Note: Special Issue on Large-Scale Parallel Processing.
Parallel Process. Lett., 2014

LSPP Introduction and Committees.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

2013
Guest Editors' note: Large-Scale Parallel Processing.
Parallel Process. Lett., 2013

Search-Based Automatic Code Generation for Multiprecision Modular Exponentiation on Multiple Generations of GPU.
Parallel Process. Lett., 2013

A dynamic adaptive converter and management for PRAM-based main memory.
Microprocess. Microsystems, 2013

Characterizing the microarchitectural side effects of operating system calls.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Toward Automatic Optimized Code Generation for Multiprecision Modular Exponentiation on a GPU.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2012
A Pattern Adaptive NAND Flash Memory Storage Structure.
IEEE Trans. Computers, 2012

LSPP Introduction.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011
Guest Editor's Note: Large-Scale Parallel Processing.
Parallel Process. Lett., 2011

High Precision Integer Multiplication with a GPU Using Strassen's Algorithm with Multiple FFT Sizes.
Parallel Process. Lett., 2011

A hybrid flash translation layer design for SLC-MLC flash memory based multibank solid state disk.
Microprocess. Microsystems, 2011

NSF/IEEE-TCPP curriculum initiative on parallel and distributed computing: core topics for undergraduates.
Proceedings of the 42nd ACM technical symposium on Computer science education, 2011

High Precision Integer Multiplication with a GPU.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Parallel multiple precision division by a single precision divisor.
Proceedings of the 18th International Conference on High Performance Computing, 2011

2010
Guest Editor's Note: Large-Scale Parallel Processing.
Parallel Process. Lett., 2010

High Precision Integer Addition, Subtraction and Multiplication with a Graphics Processing Unit.
Parallel Process. Lett., 2010

An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing.
J. Parallel Distributed Comput., 2010

High precision integer multiplication with a graphics processing unit.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

2009
A Profile-Based Multimedia Sharing Scheme With Virtual Community, Based on Personal Space in a Ubiquitous Computing Environment.
IEEE Trans. Multim., 2009

Sub-grouped superblock management for high-performance flash storages.
IEICE Electron. Express, 2009

A parallel motion estimation engine for H.264 encoding using the UMHexagonS algorithm.
Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009

2008
An effective vertical handoff scheme based on service management for ubiquitous computing.
Comput. Commun., 2008

CASL: A rapid-prototyping language for modern micro-architectures.
Comput. Lang. Syst. Struct., 2008

Towards universal code generator generation.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A Multi-Block Interleaving Structure for NAND Flash Memory Storage.
Proceedings of the 2008 International Conference on Computer Design, 2008

2007
Modeling Modern Micro-architectures using CASL.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2005
CISL: A Class-Based Machine Description Language for Co-Generation of Compilers and Simulators.
Int. J. Parallel Program., 2005

2004
CMDL: A Class-Based Machine Description Language for Co-generation of Compilers and Simulators.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003
Exploration of the Performance of a Data Mining Application via Hardware Based Monitoring.
J. Supercomput., 2003

An Intelligent Cache System with Hardware Prefetching for High Performance.
IEEE Trans. Computers, 2003

Guided Region Prefetching: A Cooperative Hardware/Software Approach.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

The CoGenT Project: Co-Generating Compilers and Simulators for Dynamically Compiled Languages.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
Application-adaptive intelligent cache memory system.
ACM Trans. Embed. Comput. Syst., 2002

Performance analysis of a selectively compressed memory system.
Microprocess. Microsystems, 2002

A banked-promotion translation lookaside buffer system.
J. Syst. Archit., 2002

A Low Power TLB Structure for Embedded Systems.
IEEE Comput. Archit. Lett., 2002

Using the Compiler to Improve Cache Replacement Decisions.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001
Guest Editor's Introduction, Special Issue: International Parallel and Distributed Processing Symposium 2000.
J. Parallel Distributed Comput., 2001

1999
The spring scheduling coprocessor: a scheduling accelerator.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Using Emulations to Enhance the Performance of Parallel Architectures.
IEEE Trans. Parallel Distributed Syst., 1999

1998
Heterogeneous Programming with Java: Gourmet Blend or Just a Hill of Beans?
Proceedings of the Seventh Heterogeneous Computing Workshop, 1998

1997
Preprototyping SIMD Coprocessors Using Virtual Machine Emulation and Trace Compilation.
Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 1997

1996
Real-Time Considerations in the Design of the Image Understanding Architecture.
Real Time Imaging, 1996

1995
Enpassant: An Environment for Evaluating Massively Parallel Array Architectures for Spatially Mapped Applications.
Int. J. Pattern Recognit. Artif. Intell., 1995

Compiler Architectures for Heterogeneous Systems.
Proceedings of the Languages and Compilers for Parallel Computing, 1995

Experimental Analysis of Some SIMD Array Memory Hierarchies.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

An empirical study of datapath, memory hierarchy, and network in SIMD array architectures.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994
Practical Algorithms for Online Routing on Fixed and Reconfigurable Meshes.
J. Parallel Distributed Comput., 1994

Associative Processing and Processors - Guest Editors' Introduction.
Computer, 1994

1993
Report on Workshop on High Performance Computing and Communications for Grand Challenge Applications: Computer Vision, Speech and Natural Language Processing, and Artificial Intelligence.
IEEE Trans. Knowl. Data Eng., 1993

The Spring Scheduling Co-Processor: Design, Use, and Performance.
Proceedings of the Real-Time Systems Symposium. Raleigh-Durham, NC, USA, December 1993, 1993

The Spring Scheduling Co-Processor: A Scheduling Accelerator.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Parallel dense depth-from-motion on the image understanding architecture.
Proceedings of the Conference on Computer Vision and Pattern Recognition, 1993

1992
Next generation architectures integrating sensory and symbolic processing.
Mach. Vis. Appl., 1992

Nonuniform region processing on SIMD arrays using the coterie network.
Mach. Vis. Appl., 1992

Image Understanding Architecture: Exploiting Potential Parallelism in Machine Vision.
Computer, 1992

1991
Message-passing algorithms for a SIMD torus with coteries.
SIGARCH Comput. Archit. News, 1991

Architectural requirements of image understanding with respect to parallel processing.
Proc. IEEE, 1991

The DARPA Image Understanding Benchmark for Parallel Computers.
J. Parallel Distributed Comput., 1991

Parallel Processing in the DARPA Strategic Computing Vision Program.
IEEE Expert, 1991

Multi-associativity: A Framework for Solving Multiple Non-uniform Problem Instances Simultaneously on SIMD Arrays.
Proceedings of the International Conference on Parallel Processing, 1991

A computational framework and SIMD algorithms for low-level support of intermediate level vision processing.
Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 1991

1990
An overview of architecture research for image understanding at the University of Massachusetts.
Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

The IUA feedback concentrator.
Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

Routing on the CAAPP.
Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

A multiple-level heterogeneous architecture for image understanding.
Proceedings of the Application Specific Array Processors, 1990

A feedback concentrator for the Image Understanding Architecture.
Proceedings of the Application Specific Array Processors, 1990

1989
The image understanding architecture.
Int. J. Comput. Vis., 1989

1988
IU parallel processing benchmark.
Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 1988

1983
Determination of the Rotational and Translational Components of a Flow Field Using a Content Addressable Parallel Processor.
Proceedings of the International Conference on Parallel Processing, 1983


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