Chaolong Xu

According to our database, Chaolong Xu authored at least 6 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator.

Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE.

Xiaoyue Hu, Fangxu Lv, Mingche Lai, Zhang Luo, Qiang Wang, Chaolong Xu, Ruotian Yin, Zhouhao Yang, Cewen Liu

IEICE Electron. Express, 2024

FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver.

Chaolong Xu, Fangxu Lv, Zhengbin Pang, Liquan Xiao, Zhouhao Yang

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023

A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks.

Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu

Proceedings of the IEEE International Conference on High Performance Computing & Communications, 2023

2022

A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.

Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi

Microelectron. J., 2022

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication.

Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu

IEEE Access, 2022