Chaolin Rao

According to our database, Chaolin Rao authored at least 13 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

FPGA Accelerator for Human Activity Recognition Based on Radar.

Kangjie Long, Chaolin Rao, Xiangyu Zhang, Wenbin Ye, Xin Lou

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

A 0.59μJ/pixel High-throughput Energy-efficient Neural Volume Rendering Accelerator on FPGA.

Zhechen Yuan, Binzhe Yuan, Yuhan Gu, Yueyang Zheng, Yunxiang He, Xuexin Wang, Chaolin Rao, Pingqiang Zhou, Jingyi Yu, Xin Lou

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

Analysis and Design of Precision-Scalable Computation Array for Efficient Neural Radiance Field Rendering.

Kangjie Long, Chaolin Rao, Yunxiang He, Zhechen Yuan, Pingqiang Zhou, Jingyi Yu, Xin Lou

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

Low-Power Reconfigurable FIR Filter Design Based on Common Operation Sharing.

Ling Zhang, Chaolin Rao, Xin Lou

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation.

Chaolin Rao, Qing Wu, Pingqiang Zhou, Jingyi Yu, Yuyao Zhang, Xin Lou

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023

A Systolic Array with Activation Stationary Dataflow for Deep Fully-Connected Networks.

Haochuan Wan, Chaolin Rao, Yueyang Zheng, Pingqiang Zhou, Xin Lou

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

ICARUS: A Specialized Architecture for Neural Radiance Fields Rendering.

Chaolin Rao, Huangjie Yu, Haochuan Wan, Jindong Zhou, Yueyang Zheng, Minye Wu, Yu Ma, Anpei Chen, Binzhe Yuan, Pingqiang Zhou, Xin Lou, Jingyi Yu

ACM Trans. Graph., 2022

ICARUS: A Lightweight Neural Plenoptic Rendering Architecture.

Chaolin Rao, Huangjie Yu, Haochuan Wan, Jindong Zhou, Yueyang Zheng, Yu Ma, Anpei Chen, Minye Wu, Binzhe Yuan, Pingqiang Zhou, Xin Lou, Jingyi Yu

CoRR, 2022

An RRAM-based Neural Radiance Field Processor.

Yueyang Zheng, Chaolin Rao, Haochuan Wan, Yuliang Zhou, Pingqiang Zhou, Jingyi Yu, Xin Lou

Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

A Multi-precision Multiply-Accumulation Array.

Chaolin Rao, Yueyang Zheng, Haochuan Wan

Proceedings of the 19th International SoC Design Conference, 2022

SME: A Systolic Multiply-accumulate Engine for MLP-based Neural Network.

Haochuan Wan, Chaolin Rao, Yueyang Zheng, Pingqiang Zhou, Xin Lou

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

An Energy Efficient Precision Scalable Computation Array for Neural Radiance Field Accelerator.

Chaolin Rao, Haochuan Wan, Yueyang Zheng, Pingqiang Zhou, Xin Lou

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

FPGA Accelerator for Radar-Based Human Activity Recognition.

Kangjie Long, Chaolin Rao, Xiangyu Zhang, Wen Bin Ye, Xin Lou

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022