Chaofeng Yu

Orcid: 0000-0002-0558-6683

According to our database1, Chaofeng Yu authored at least 5 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2025
Verifying chip designs at RTL level.
Sci. Comput. Program., 2025

2023
A proof system for unified temporal logic.
Theor. Comput. Sci., March, 2023

Wavelet-Based Time-Reassigned Synchroextracting Transform With Application to Fault Diagnosis of Flexible Thin-Wall Bearing.
IEEE Trans. Instrum. Meas., 2023

Verifying Chips Design at RTL Level.
Proceedings of the Theoretical Aspects of Software Engineering, 2023

An Approach to Agent Path Planning Under Temporal Logic Constraints.
Proceedings of the Computing and Combinatorics - 29th International Conference, 2023


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